AT32UC3A0128AU Atmel Corporation, AT32UC3A0128AU Datasheet - Page 563
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AT32UC3A0128AU
Manufacturer Part Number
AT32UC3A0128AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
6.AT32UC3A0128AU.pdf
(2 pages)
Specifications of AT32UC3A0128AU
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
109
Ext Interrupts
109
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0128AU-U
Manufacturer:
ATMEL
Quantity:
4
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
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- AT32UC3A0128 PDF datasheet #5
- AT32UC3A0128AU PDF datasheet #6
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32058K AVR32-01/12
30.8.2.5
Offset:
Register Name:
Access Type:
Reset Value:
• SUSPE: Suspend Interrupt Enable
Set by software (by setting the SUSPES bit) to enable the Suspend interrupt (SUSP).
Clear by software (by setting the SUSPEC bit) to disable the Suspend interrupt (SUSP).
• SOFE: Start of Frame Interrupt Enable
Set by software (by setting the SOFES bit) to enable the Start of Frame interrupt (SOF).
Clear by software (by setting the SOFEC bit) to disable the Start of Frame interrupt (SOF).
• EORSTE: End of Reset Interrupt Enable
Set by software (by setting the EORSTES bit) to enable the End of Reset interrupt (EORST).
Clear by software (by setting the EORSTEC bit) to disable the End of Reset interrupt (EORST).
• WAKEUPE: Wake-Up Interrupt Enable
Set by software (by setting the WAKEUPES bit) to enable the Wake-Up interrupt (WAKEUP).
Clear by software (by setting the WAKEUPEC bit) to disable the Wake-Up interrupt (WAKEUP).
• EORSME: End of Resume Interrupt Enable
Set by software (by setting the EORSMES bit) to enable the End of Resume interrupt (EORSM).
Clear by software (by setting the EORSMEC bit) to disable the End of Resume interrupt (EORSM).
• UPRSME: Upstream Resume Interrupt Enable
Set by software (by setting the UPRSMES bit) to enable the Upstream Resume interrupt (UPRSM).
Clear by software (by setting the UPRSMEC bit) to disable the Upstream Resume interrupt (UPRSM).
EP3INTE
31
23
15
–
0
7
–
r
USB Device Global Interrupt Enable Register (UDINTE)
DMA6INTE
UPRSME
EP2INTE
30
22
14
0
–
0
6
0
r
r
r
DMA5INTE
EORSME
EP1INTE
29
21
13
0
–
0
5
0
r
r
r
0x0010
UDINTE
Read-Only
0x00000000
DMA4INTE
WAKEUPE
EP0INTE
28
20
12
0
0
4
0
r
r
r
DMA3INTE
EORSTE
27
19
11
0
–
3
0
r
r
DMA2INTE
EP6INTE
SOFE
26
18
10
0
0
–
2
0
r
r
r
DMA1INTE
EP5INTE
25
17
0
0
9
–
1
–
r
r
AT32UC3A
EP4INTE
SUSPE
24
16
–
0
8
–
0
0
r
r
563
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