AT32UC3A0128AU Atmel Corporation, AT32UC3A0128AU Datasheet - Page 115
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AT32UC3A0128AU
Manufacturer Part Number
AT32UC3A0128AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
6.AT32UC3A0128AU.pdf
(2 pages)
Specifications of AT32UC3A0128AU
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
109
Ext Interrupts
109
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0128AU-U
Manufacturer:
ATMEL
Quantity:
4
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32058K AVR32-01/12
18. Flash Controller (FLASHC)
18.1
18.2
18.3
18.3.1
18.3.2
Features
Description
Product dependencies
Power management
Interrupt
Rev: 2.0.0.2
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The flash controller (FLASHC) interfaces a flash block with the 32-bit internal HSB bus. Perfor-
mance for uncached systems with high clock-frequency and one wait state is increased by
placing words with sequential addresses in alternating flash subblocks. Having one read inter-
face per subblock allows them to be read in parallel. While data from one flash subblock is
being output on the bus, the sequential address is being read from the other flash subblock
and will be ready in the next clock cycle.
The controller also manages the programming, erasing, locking and unlocking sequences with
dedicated commands.
T h e H F L A S H C h a s t w o b u s c l o c k s c o n n e c t e d : O n e H i g h s p e e d b u s c l o c k
(CLK_FLASHC_HSB) and one Peripheral bus clock (CLK_FLASHC_PB). These clocks are
generated by the Power manager. Both clocks are turned on by default, but the user has to
ensure that CLK_FLASHC_HSB is not turned off before reading the flash or writing the page-
buffer and that CLK_FLASHC_PB is not turned of before accessing the FLASHC configuration
and control registers.
The FLASHC interrupt lines are connected to internal sources of the interrupt controller. Using
FLASHC interrutps requires the interrupt controller to be programmed first.
Controls flash block with dual read ports allowing staggered reads.
Supports 0 and 1 wait state bus access.
Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per
clock cycle.
32-bit HSB interface for reads from flash array and writes to page buffer.
32-bit PB interface for issuing commands to and configuration of the controller.
16 lock bits, each protecting a region consisting of (total number of pages in the flash block /
16) pages.
Regions can be individually protected or unprotected.
Additional protection of the Boot Loader pages.
Supports reads and writes of general-purpose NVM bits.
Supports reads and writes of additional NVM pages.
Supports device protection through a security bit.
Dedicated command for chip-erase, first erasing all on-chip volatile memories before erasing
flash and clearing security bit.
Interface to Power Manager for power-down of flash-blocks in sleep mode.
AT32UC3A
115
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