AT32UC3A0128AU Atmel Corporation, AT32UC3A0128AU Datasheet - Page 516
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AT32UC3A0128AU
Manufacturer Part Number
AT32UC3A0128AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
6.AT32UC3A0128AU.pdf
(2 pages)
Specifications of AT32UC3A0128AU
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
109
Ext Interrupts
109
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0128AU-U
Manufacturer:
ATMEL
Quantity:
4
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32058K AVR32-01/12
30.7.2.12
30.7.2.12.1 Overview
Figure 30-17. Example of an IN Endpoint with 1 Data Bank
TXINI
FIFOCON
Management of IN Endpoints
SW
The OUT retry is always ACKed. This reception sets RXOUTI and TXINI. Handle this with the
following software algorithm:
Once the OUT status stage has been received, the USB controller waits for a SETUP request.
The SETUP request has priority over any other request and has to be ACKed. This means that
any other flag should be cleared and the FIFO reset when a SETUP is received.
The firmware has to take care of the fact that the byte counter is reset when a zero-length OUT
packet is received.
IN packets are sent by the USB device controller upon IN requests from the host. All the data
can be written by the firmware which acknowledges or not the bank when it is full.
The endpoint must be configured first.
The TXINI bit is set by hardware at the same time as FIFOCON when the current bank is free.
This triggers an EPXINT interrupt if TXINE = 1.
TXINI shall be cleared by software (by setting the TXINIC bit) to acknowledge the interrupt, what
has no effect on the endpoint FIFO.
The firmware then writes into the FIFO and clears the FIFOCON bit to allow the USB controller
to send the data. If the IN endpoint is composed of multiple banks, this also switches to the next
bank. The TXINI and FIFOCON bits are updated by hardware in accordance with the status of
the next bank.
TXINI shall always be cleared before clearing FIFOCON.
The RWALL bit is set by hardware when the current bank is not full, i.e. the software can write
further data into the FIFO.
write data to CPU
NAK
set TXINI
wait for RXOUTI OR TXINI
if RXOUTI, then clear flag and return
if TXINI, then continue
BANK 0
SW
IN
(bank 0)
DATA
HW
ACK
SW
write data to CPU
BANK 0
AT32UC3A
SW
IN
516
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