AT32UC3A0128AU Atmel Corporation, AT32UC3A0128AU Datasheet - Page 378
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AT32UC3A0128AU
Manufacturer Part Number
AT32UC3A0128AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
6.AT32UC3A0128AU.pdf
(2 pages)
Specifications of AT32UC3A0128AU
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
109
Ext Interrupts
109
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0128AU-U
Manufacturer:
ATMEL
Quantity:
4
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27.6.4.3
27.6.4.4
– NWE Waveforms
Write Waveforms
NCS Waveforms
Figure 27-12. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS
The write protocol is similar to the read protocol. It is depicted in
starts with the address setting on the memory address bus.
The NWE signal is characterized by a setup timing, a pulse width and a hold timing.
1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before
2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE
3. NWE_HOLD: The NWE hold time is defined as the hold time of address and data after
The NWE waveforms apply to all byte-write lines in Byte Write access mode: NWR0 to NWR3.
The NCS signal waveforms in write operation are not the same that those applied in read opera-
tions, but are separately defined:
1. NCS_WR_SETUP: the NCS setup time is defined as the setup time of address before
2. NCS_WR_PULSE: the NCS pulse length is the time between NCS falling edge and NCS
3. NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the
NBS0, NBS1,
the NWE falling edge;
rising edge;
the NWE rising edge.
the NCS falling edge.
rising edge;
NCS rising edge.
A0, A1
CLK_SMC
D[15:0]
A[25:2]
NRD
NCS
t
PACC
Data Sampling
Figure
27-13. The write cycle
AT32UC3A
378
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