AT32UC3A0128AU Atmel Corporation, AT32UC3A0128AU Datasheet - Page 412

• Manufacturer Part Number: AT32UC3A0128AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0128AU

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
28.5
28.5.1
Figure 28-2. SDRAM Controller Connections to SDRAM Devices: 32-bit Data Bus Width
Figure 28-3. SDRAM Controller Connections to SDRAM Devices: 16-bit Data Bus Width
Application Example
Hardware Interface
Controller
Controller
SDRAM
SDRAM
SDRAMC_A[0-12]
SDRAMC_A[0-12]
D0-D31
SDCKE
SDWE
NBS3
SDCS
SDCK
NBS0
NBS1
NBS2
D0-D31
SDCKE
RAS
CAS
BA0
BA1
SDWE
SDCS
SDCK
NBS0
NBS1
RAS
CAS
BA0
BA1
Figure 28-2
32-bit data bus width.
bit data bus width. It is important to note that these examples are given for a direct connection of
the devices to the SDRAM Controller, without External Bus Interface or PIO Controller
multiplexing.
D16-D23
D0-D7
SDWE
NBS0
SDWE
NBS2
shows an example of SDRAM device connection to the SDRAM Controller using a
D0-D7
SDWE
NBS0
D0-D7
CS
CLK
CKE
WE
RAS
CAS
DQM
D0-D7
CS
CLK
CKE
WE
RAS
CAS
DQM
D0-D7
CS
CLK
CKE
WE
RAS
CAS
DQM
SDRAM
SDRAM
2M x 8
2M x 8
SDRAM
2M x 8
A0-A9, A11
A0-A9, A11
Figure 28-3
A0-A9, A11
BA0
BA1
BA0
BA1
A10
A10
BA0
BA1
A10
SDRAMC_A[0-9], SDRAMC_A11
SDRAMC_A10
BA0
BA1
SDRAMC_A[0-9], SDRAMC_ A11
SDRAMC_A10
BA0
BA1
SDRAMC_A[0-9], SDRAMC_A11
SDRAMC_A10
BA0
BA1
shows an example of SDRAM device connection using a 16-
D24-D31
D8-D15
SDWE
SDWE
NBS3
NBS1
D8-D15
SDWE
NBS1
D0-D7
CS
CLK
CKE
WE
RAS
CAS
DQM
D0-D7
CS
CLK
CKE
WE
RAS
CAS
DQM
D0-D7
CS
CLK
CKE
WE
RAS
CAS
DQM
SDRAM
SDRAM
2M x 8
2M x 8
SDRAM
2M x 8
A0-A9, A11
A0-A9, A11
A0-A9, A11
BA0
BA1
A10
A10
BA0
BA1
BA0
BA1
A10
SDRAMC_A[0-9], SDRAMC_A11
SDRAMC_A10
BA0
BA1
SDRAMC_A[0-9], SDRAMC_A11
SDRAMC_A10
BA0
BA1
SDRAMC_A[0-9], SDRAMC_A11
SDRAMC_A10
BA0
BA1
AT32UC3A
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