DS3510T+T&R Maxim Integrated Products, DS3510T+T&R Datasheet - Page 5

• Manufacturer Part Number: DS3510T+T&R
• Description: IC I2C GAMMA/VCOM BUFF 48-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of DS3510T+T&R

• Applications: TFT-LCD Panels: Gamma Buffer, VCOM Driver
• Output Type: Rail-to-Rail
• Number Of Circuits: 10
• Current - Supply: 6.7mA
• Current - Output / Channel: 4mA
• Voltage - Supply, Single/dual (±): 9 V ~ 15 V
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NONVOLATILE MEMORY CHARACTERISTICS
(V CC = +2.7V to +5.5V.)
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: Tested at VRL = VRH = 6.5V/7.5V/8.5V, GLL = GLM = 0.5V/6.5V/8.5V/14.5V, GHM = GHH = 0.5V/6.5V/8.5V/14.5V.
Note 11: EEPROM data is assumed already settled at input of Latch B. LD transitions after EEPROM byte has been selected.
Note 12: Rising transition from 5V to 10V; falling transition from 10V to 5V.
Note 13: I
Note 14: C
Note 15: EEPROM write time begins after a STOP condition occurs.
Note 16: Pulses narrower than max are suppressed.
Figure 1. V
EEPROM Write Cycles
EEPROM Write Cycles
S0/S1
V
COM
LD
All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are
negative.
I
Specified with the V
I
I
I
Guaranteed by design.
Integral nonlinearity is the deviation of a measured value from the expected values at each particular setting. Expected
value is calculated by connecting a straight line from the measured minimum setting to the measured maximum setting.
INL = [V(RW)
Differential nonlinearity is the deviation of the step size change between two LSB settings from the expected step size. The
expected LSB step size is the slope of the straight line from measured minimum position to measured maximum position.
DNL = [V(RW)
standard mode timing.
PARAMETER
COM
DD
CC
CCQ
DDQ
2
C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I
B
—total capacitance of one bus line in picofarads.
I
supply current is specified with V
is specified with the following conditions: SCL = 400kHz, SDA = V
V
2
is specified with the following conditions: SCL = SDA = V
is specified with the following conditions: SCL = SDA = V
Settling Timing Diagram
IL
C Gamma and V
_______________________________________________________________________________________
t
HD
i
- (V(RW)
i+1
- (V(RW)
COM
0
V
V
]/LSB(measured) - i, for i = 0...255.
IH
IL
t
and gamma bias currents set to 100%.
SU
V
i
SYMBOL
]/LSB(measured) - 1, for i = 0...254.
IH
DD
T
T
A
A
= 15.0V and no load on V
= +70°C
= +25°C
t
SET-V
COM
CONDITIONS
CC
CC
= 5.5V, and V
= 5.5V and V
COM
Buffer with EEPROM
CC
or GM1–10 outputs.
= 5.5V, and V
COM
COM
0.1% SETTLED
and GM1–10 floating.
and GM1–10 floating.
COM
200,000
50,000
MIN
and GM1–10 floating.
V
COM
MAX
2Ω
2
C
100nF
UNITS
Writes
Writes
5