DS3510 Maxim Integrated Products, DS3510 Datasheet

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DS3510

Manufacturer Part Number
DS3510
Description
Manufacturer
Maxim Integrated Products
Datasheet
The DS3510 is a programmable gamma and V
age generator which supports both real-time updating
as well as multibyte storage of gamma/V
chip EEPROM memory. An independent 8-bit DAC, two
8-bit data registers, and 4 bytes of EEPROM memory
are provided for each individually addressable gamma
or V
are integrated on-chip, providing rail-to-rail, low-power
(400µA/gamma channel) operation. The V
features a high-current drive (> 250mA peak) and a fast-
settling buffer amplifier optimized to drive the V
node of a wide range of TFT-LCD panels.
Programming occurs through an I
interface. Interface performance and flexibility are
enhanced by a pair of independently loaded data reg-
isters per channel, as well as support for I
to 400kHz. The multitable EEPROM memory enables a
rich variety of display system enhancements, including
support for temperature or light-level-dependent
gamma tables, enabling of factory or field automated
display adjustment, and support for backlight dimming
algorithms to reduce system power. Upon power-up
and depending on mode, DAC data is selected from
EEPROM by the S0/S1 pads or from a fixed memory
address.
Rev 0; 2/08
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
SDA, SCL
S1/ S0
COM
A0
LD
TFT-LCD Gamma and V
Adaptive Gamma and V
Time by I
S0/S1 Pads)
Industrial Process Control
channel. High-performance buffer amplifiers
I
2
2
INTERFACE
C Gamma and V
C, Select EEPROM Through I
________________________________________________________________ Maxim Integrated Products
LOGIC
I
2
C
General Description
COM
COM
LATCH A
2
Applications
Buffer
Adjustment (Real-
C-compatible serial
COM
2
COM
C speeds up
Gamma or V
data in on-
2
COM
IN
ADDRESS
C or
channel
EEPROM
COM
volt-
COM
OUT
♦ 8-Bit Gamma Buffers, 10 Channels
♦ 8-Bit V
♦ 4 EEPROM Bytes per Channel
♦ Low-Power 400µA/ch Gamma Buffers
♦ I
♦ Flexible Control from I
♦ 9.0V to 15.0V Analog Supply
♦ 2.7V to 5.5V Digital Supply
♦ 48-Pin Package (TQFN 7mm x 7mm)
+ Denotes a lead-free package.
T&R = Tape and reel.
*EP = Exposed pad.
Pin Configuration and Typical Operating Circuit appear at
end of data sheet.
DS3510T+
DS3510T+T&R -45°C to +95°C
COM
2
C-Compatible Serial Interface
PART
Buffer with EEPROM
MUX
COM
Channel Functional Diagram
Buffer, 1 Channel
-45°C to +95°C
TEMP RANGE
LATCH B
Ordering Information
2
C or Pins
8-BIT
DAC
PIN-
PACKAGE
48 TQFN-EP*
48 TQFN-EP*
Features
T4877+6
T4877+6
CODE
PKG
V
OUT
1

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DS3510 Summary of contents

Page 1

... Rev 0; 2/ Gamma and V General Description The DS3510 is a programmable gamma and V age generator which supports both real-time updating as well as multibyte storage of gamma/V chip EEPROM memory. An independent 8-bit DAC, two 8-bit data registers, and 4 bytes of EEPROM memory are provided for each individually addressable gamma or V channel ...

Page 2

I C Gamma and V ABSOLUTE MAXIMUM RATINGS Voltage on V Relative to GND ............................-0.5V to +16V DD Voltage on VRL, VRH, GHH, GHM, GLM, GLL Relative to GND........-0. 0.5V), not to exceed 16V DD Voltage ...

Page 3

I C Gamma and V INPUT ELECTRICAL CHARACTERISTICS (continued +2.7V to +5.5V -45°C to +95°C, unless otherwise noted PARAMETER SYMBOL R Tolerance TOTAL Input Resistance (GHH, GHM, GLM, GLL) Input Resistance Tolerance OUTPUT ...

Page 4

I C Gamma and ELECTRICAL CHARACTERISTICS (See Figure +2.7V to +5.5V -45°C to +95°C, timing referenced PARAMETER SYMBOL SCL Clock Frequency Bus Free Time Between STOP ...

Page 5

I C Gamma and V NONVOLATILE MEMORY CHARACTERISTICS ( +2.7V to +5.5V.) PARAMETER SYMBOL EEPROM Write Cycles EEPROM Write Cycles Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive and currents ...

Page 6

I C Gamma and S0/ GM1–10 Figure 2. GM1–10 Settling Timing Diagram V S0/ GM1–GM10 Figure 3. ...

Page 7

I C Gamma and +25°C, unless otherwise noted vs 180 +25°C 160 +95°C 140 120 -40°C 100 80 60 2.7 3.2 3.7 4.2 4.7 5 vs. V ...

Page 8

... I C Serial Clock Input 2 C Serial Data Input/Output 2 Address Input. This pin determines I C slave address of the DS3510. Digital Supply (2.7V to 5.5V) V Reference Inputs. High-voltage reference for V COM No Connection Compensation Capacitor Input. Connect VCAP to GND through a 0.1μF capacitor. References for Low-Voltage Gamma DAC ...

Page 9

... I C Gamma and V BANKS GM10 BANK A DS3510 GM10 BANK B GM10 BANK C GM10 BANK D S0/S1 PINS S0/S1 BITS COMP BANKS GM6 BANK A GM6 BANK B GM6 BANK C GM6 BANK D S0/S1 PINS S0/S1 BITS SDA 2 COMP SCL I C INTERFACE A0 BANKS VCOM BANK A VCOM BANK B VCOM BANK C MODE0 BIT (CR ...

Page 10

... DAC output. A detailed description of the three modes as well as additional features of the DS3510 follows. The DS3510 mode of operation is determined by 2 bits located in the Control register (60h), which is non- volatile (NV) (EEPROM). In particular, the mode is determined by the MODE0 bit (CR.0) and the MODE1 bit (CR ...

Page 11

... Slave Address Byte and Address Pin channel is The slave address byte consists of a 7-bit slave COM address plus a R/W bit (see Figure 5). The DS3510’s slave address is determined by the state of the A0 pin. This pin allows up to two devices to reside on the same bus ...

Page 12

... I C Gamma and V Memory Organization Memory Description The list of registers/memory contained in the DS3510 is shown in the Memory Map . Also shown for each of the registers is the memory type and accessibility, as well as the power-up default values for volatile locations and ADDR NAME (HEX) V Latch A ...

Page 13

I C Gamma and V SOFT S0/S1 50h: SOFT S1/S0 Bits FACTORY DEFAULT MEMORY TYPE 50h x x bit7 bit7:2 Reserved These bits are used when in SOFT S0/S1 (bit) Controlled Bank Updating Mode (MODE1 = 0, MODE0 = ...

Page 14

... COM 00 = 150% bit5 100% (default 80 60% bits3:2 Reserved DS3510 Mode S0/S1 Pins are Used to Select the Desired Bank (A–D) (Default) bits1 Soft S0/S1 (Bits) Are Used to Select the Desired Bank (A– Latch A Is Used to Control the DACs Serial Interface Description The following terminology is commonly used to describe 2 C data transfers ...

Page 15

... STOP condition. Remember the master must read the slave’s acknowledgment during all byte write operations. When writing to the DS3510 (and 1), the DAC will adjust to the new setting once it has acknowledged the new data that is being written, and the EEPROM (used to make the setting nonvolatile) will be written following the STOP condition at the end of the write command ...

Page 16

... START READ 10h AND 11h 2 Figure Communication Examples EEPROM write cycles: The DS3510’s EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature (hot) as well as at room tem- perature. ...

Page 17

... I C Gamma and V Applications Information Power-Supply Decoupling To achieve the best results when using the DS3510, decouple all the power-supply pins (V 0.01µF or 0.1µF capacitor. Use a high-quality ceramic surface-mount capacitor if possible. Surface-mount com- ponents minimize lead inductance, which improves per- formance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications ...

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