DS3510T+T&R Maxim Integrated Products, DS3510T+T&R Datasheet - Page 10

• Manufacturer Part Number: DS3510T+T&R
• Description: IC I2C GAMMA/VCOM BUFF 48-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of DS3510T+T&R

• Applications: TFT-LCD Panels: Gamma Buffer, VCOM Driver
• Output Type: Rail-to-Rail
• Number Of Circuits: 10
• Current - Supply: 6.7mA
• Current - Output / Channel: 4mA
• Voltage - Supply, Single/dual (±): 9 V ~ 15 V
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
The DS3510 operates in one of three modes which
determine how the V
trolled/updated. The first two modes allow “banked”
control of the 10 gamma channels and 1 V
nel. Depending on the mode, one of four banks (in
EEPROM) can be selected using either the S0/S1 pins
or using the SOFT S0/S1 bits in the Soft S0/S1 register.
Once a bank is selected, the LD pin can then be used
to simultaneously update each channel’s DAC output.
The third and final mode is not banked. It allows I
control of each channel’s Latch A register which is
SRAM (volatile), allowing quick and unlimited updates.
In this mode, the LD pin can also be used to simultane-
ously update each channel’s DAC output. A detailed
description of the three modes as well as additional
features of the DS3510 follows.
The DS3510 mode of operation is determined by 2 bits
located in the Control register (60h), which is non-
volatile (NV) (EEPROM). In particular, the mode is
determined by the MODE0 bit (CR.0) and the MODE1
bit (CR.1). Table 1 illustrates how the 2 control bits are
used to select the operating mode. When shipped from
the factory, the DS3510 is programmed with both
MODE bits set to zero.
Table 1. DS3510 Operating Modes
As shown in the block diagram, each channel contains
4 bytes of EEPROM, which are used to implement the
“banking” functionality. Each “bank” contains unique
DAC settings for each channel. When the DS3510 is
configured in this operating mode, the desired bank is
selected using the S0 and S1 pins as shown in Table 2
where 0 is ground and 1 is V
S1 are both connected to ground, then the first bank
(Bank A) is selected. Once a bank is selected, the tim-
ing of the DAC update depends on the state of LD pin.
When LD is high, Latch B functions as a flow-through
latch, so the amplifier will respond asynchronously to
10
MODE1 BIT
2
S0/S1 Pin-Controlled Bank Updating Mode
(CR.1)
C Gamma and V
______________________________________________________________________________________
0
0
1
MODE0 BIT
(CR.0)
X
0
1
COM
Detailed Description
and gamma DACs are con-
CC
S0/S1 Pin-Controlled Bank
Updating (Factory Default)
S0/S1 Bit-Controlled Bank
Updating
I
Control
2
C Individual Channel
. For example, if S0 and
Mode Selection
MODE
COM
COM
chan-
2
C
Buffer with EEPROM
changes in the state of S0/S1 to meet the t
cation. Conversely, when LD is low, Latch B functions
as a latch, holding its previous data. A low-to-high tran-
sition on LD allows the Latch B input data to flow
through and update the DACs with the EEPROM bank
selected by S0/S1. A high-to-low transition on LD latch-
es the selected DAC data into Latch B.
This mode also features “banked” operation with the
only difference being how the desired bank is selected.
In particular, the bank is selected using the SOFT S0
(bit 0) and SOFT S1 (bit 1) bits contained in the Soft
S0/S1 register (50h). The S0 and S1 pins are ignored in
this mode. Table 2 illustrates the relationship between
the bit settings and the selected bank. For example, if
both bits, S0 and S1, are written to zero, then the first
bank (Bank A) is selected. Once a bank is selected, the
timing of the DAC update depends on the state of the
LD pin. When LD is high, Latch B functions as a flow-
through latch, so the amplifier will respond asynchro-
nously to changes in the state of the S0/S1 bits. These
are changed by an I
low, Latch B functions as a latch, holding its previous
data. A low-to-high transition on LD allows the Latch B
input data to flow through and update the DACs with
the EEPROM bank selected by the S0/S1 bits. A high-
to-low transition on LD latches the selected DAC data
into Latch B.
Since the Soft S0/S1 register is SRAM, subsequent
power-ups result in the SOFT S0 and SOFT S1 bits
being cleared to 0 and, hence, powering up to Bank A.
In this mode the I
channel Latch A registers to update a single DAC (i.e.,
not banked). The Latch A registers are SRAM and not
EEPROM. This allows an unlimited number of write
cycles as well as quicker write times since t
applies to EEPROM writes. As shown in the Memory
Map , the Latch A registers for each channel are
accessed through memory addresses 00–0Ah. Then,
Table 2. DS3510 Bank Selection Table
S1
0
0
1
1
I
2
C Individual Channel Control Mode
S0
0
1
0
1
SOFT S0/S1 (Bit) Controlled Bank
2
C master writes directly to individual
V
V
V
V
2
COM
COM
COM
COM
CHANNEL
C write. Conversely, when LD is
V
COM
Bank A
Bank B
Bank C
Bank D
Updating Mode
GM1–10 Bank A
GM1–10 Bank B
GM1–10 Bank C
GM1–10 Bank D
CHANNELS
GAMMA
SEL
specifi-
W
only