SC28L201A1DGG,112 NXP Semiconductors, SC28L201A1DGG,112 Datasheet - Page 69

• Manufacturer Part Number: SC28L201A1DGG,112
• Description: IC UART W/FIFO 48-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L201A1DGG,112

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3293-5; 935277824112; SC28L201A1DGG

Philips Semiconductors
9397 750 13138
Product data sheet
8.5.1 Interrupt Control Register (ICR)
8.5.2 Update CIR (UCIR): the most important command for polled or interrupt
8.5 Registers of the Arbitrating Interrupt system and bidding control
Table 46:
This register provides a single 8-bit field called the interrupt threshold for use by the
interrupt arbiter. The field is interpreted as a single unsigned integer. The interrupt arbiter
will not generate an external interrupt request, by asserting IRQN, unless the value of the
highest priority interrupt exceeds the value of the interrupt threshold. If the highest bidder
in the interrupt arbitration is lower than the threshold level set by the ICR, the Current
Interrupt Register, CIR, will contain 0x00.
Remark: While a Watchdog Timer interrupt is pending, the ICR is not used and only
receiver codes are presented for interrupt arbitration. This allows receivers with very low
count values (perhaps below the threshold value) to win interrupt arbitration without
requiring the user to explicitly lower the threshold level in the ICR.
service
Table 47:
A write to address 0x61 data is not important. A command based upon a decode of a
write to address 0x61 (UCIR is not a register). A write (the write data is not important; a
‘Don’t care’) to this ‘register’ causes the Current Interrupt Register to be updated with the
value that is winning interrupt arbitration. The register would be used in systems that poll
the interrupt status registers rather than wait for interrupts. Alternatively, the CIR is
normally updated during an Interrupt Acknowledge Bus (IACKN) cycle in interrupt-driven
systems.
Bit
7:0
Bit
7:0
Symbol
Symbol
ICR - Interrupt Control Register (address 0x60) bit description
UCIR - Update CIR (address 0x61) bit description
Description
Upper 8 bits of the Arbitration Threshold
Description
data not important
Rev. 01 — 31 October 2005
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC28L201
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