SC28L201A1DGG,112 NXP Semiconductors, SC28L201A1DGG,112 Datasheet - Page 29

• Manufacturer Part Number: SC28L201A1DGG,112
• Description: IC UART W/FIFO 48-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L201A1DGG,112

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3293-5; 935277824112; SC28L201A1DGG

Philips Semiconductors
9397 750 13138
Product data sheet
7.4.8.1 Enabling and activating interrupt sources
7.4.8.2 Setting interrupt priorities
Associated with the interrupt system are the Interrupt Mask Register (IMR) and the
Interrupt Status Register (ISR) resident in each UART. Programming of the IMR selects
which of the above sources may enter the arbitration process. The IMR enables the
interrupt. Only the bidders in the ISR whose associated bit in the IMR is set to one (1) will
be permitted to enter the arbitration process. The ISR can be read by the host CPU to
determine all currently active interrupting conditions. For convenience of reading the ISR,
the MR1[6] bit, when set, allows the reading of the ISR masked by the bits of the IMR.
An interrupt source becomes enabled when writing a one to the proper Interrupt Mask
Register bit (IMR) activates its interrupt capability. An interrupt source can never generate
an IRQN or have its ‘bid’ or interrupt number appear in the CIR unless the source has
been enabled by the appropriate bit in an IMR.
An interrupt source is active if it is presenting its bid to the interrupt arbiter for evaluation.
Most sources have simple activation requirements. The watchdog timer, break received,
Xon/Xoff or Address Recognition and change-of-state interrupts become active when the
associated events occur and the arbitration value generated thereby exceeds the
threshold value programmed in the Interrupt Control Register (ICR).
The transmitter and receiver functions have additional controls to modify the condition
upon which the initiation of interrupt bidding begins: the TxINT and RxINT fields of the
MR0 and MR2 registers. These fields can be used to start bidding or arbitration when the
RxFIFO is not empty, 50 % full, 75 % full, or 100 % full. For the transmitter it is not full,
50 % empty, 75 % empty, and empty.
Example: To increase the probability of transferring the contents of a nearly full RxFIFO,
do not allow it to start bidding until 50 % or 75 % full. This will prevent its relatively high
priority from winning the arbitration process at low fill levels. A high threshold level could
accomplish the same thing, but may also mask out low priority interrupt sources that must
be serviced. Note that for fast channels and/or long interrupt latency times using this
feature should be used with caution since it reduces the time the host CPU has to respond
to the interrupt request before receiver overrun occurs.
The bid or interrupt number presented to the interrupt arbiter is composed of character
counts, channel codes, fixed and programmable bit fields. The interrupt values are
generated for various interrupt sources as shown in
bits 11:4 in
‘Threshold’, bits 10:0 of the ICR (Interrupt Control Register), is aligned such that bit 0 of
the threshold is compared to bit 1 of the interrupt value generated by any of the sources.
Whenever the value of the interrupt source is greater than the threshold the interrupt will
be generated.
The codes form bits 4:1 drive part of the interrupt vector modification and the Global
Interrupt Type Register. The codes are unique to each source type and identify them
completely.
Table 4
are compared against the value represented by the ‘Threshold’. The
Rev. 01 — 31 October 2005
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
Table
4. The value represented by the
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC28L201
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