SC28L201A1DGG,112 NXP Semiconductors, SC28L201A1DGG,112 Datasheet - Page 48

• Manufacturer Part Number: SC28L201A1DGG,112
• Description: IC UART W/FIFO 48-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L201A1DGG,112

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3293-5; 935277824112; SC28L201A1DGG

Philips Semiconductors
9397 750 13138
Product data sheet
8.2.4 Mode Register 3 (MR3)
Table 19:
Bit
7
6
5:4
3:2
Symbol
-
MR3 - Mode Register 3 (address 0x23) bit description
Description
Xon/Xoff transparency
Control the handling of recognized Xon/Xoff characters. If set, the character
codes are placed on the RxFIFO along with their status bits just as ordinary
characters are. If the character is not loaded onto the RxFIFO, its received
status will be lost unless the receiver is operating in the block error mode, see
MR1[5] and the general discussion on receiver error handling. Interrupt
processing is not effected by the setting of these bits. See
“Character and address
Address recognition transparency
Control the handling of recognized Address characters. If set, the character
codes are placed on the RxFIFO along with their status bits just as ordinary
characters are. If the character is not loaded onto the RxFIFO, its received
status will be lost unless the receiver is operating in the block error mode, see
MR1[5] and the general discussion on receiver error handling. Interrupt
processing is not effected by the setting of these bits. See
“Character and address
reserved
In-band flow control mode. Xon/Xoff processing.
Control the Xon/Xoff processing logic. Auto Transmitter flow control allows the
gating of Transmitter activity by Xon/Xoff characters received by the Channel’s
receiver. Auto Receiver flow control causes the Transmitter to emit an Xoff
character when the RxFIFO has loaded to a depth of 240 characters. Draining
the RxFIFO to a level of 128 or less causes the Transmitter to emit an Xon
character. All transmissions require no host involvement. A setting other than
00 in this field precludes the use of the command register to transmit Xon/Xoff
characters.
Remark: Interrupt generation in Xon/Xoff processing is controlled by the IMR
(Interrupt Mask Register) of the individual channels. The interrupt may be
cleared by a read of the XISR, the Xon/Xoff Interrupt Status Register. Receipt
of a flow control character will always generate an interrupt if the IMR is so
programmed. The MR0[3:2] bits have effect on the automatic aspects of flow
control only, not the interrupt generation.
0 = flow control characters received are loaded onto the RxFIFO
1 = flow control characters received are not loaded onto the RxFIFO
0 = address characters received are loaded to RxFIFO
1 = address characters are not loaded onto the RxFIFO
00 = host mode; only the host CPU may initiate flow control actions through
the CR.
01 = auto transmitter flow control
10 = auto receiver flow control
11 = auto Rx and Tx flow control
Rev. 01 — 31 October 2005
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
[1]
recognition”.
recognition”.
. Xon/Xoff character stripping.
[1]
. Xon/Xoff character stripping.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC28L201
Section 6.1.9
Section 6.1.9
48 of 110