SC28L201A1DGG,112 NXP Semiconductors, SC28L201A1DGG,112 Datasheet - Page 102
![IC UART W/FIFO 48-TSSOP](/photos/6/50/65054/568-48-tssop_sot480-1_sml.jpg)
SC28L201A1DGG,112
Manufacturer Part Number
SC28L201A1DGG,112
Description
IC UART W/FIFO 48-TSSOP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet
1.SC28L201A1DGG118.pdf
(110 pages)
Specifications of SC28L201A1DGG,112
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
256 Byte
Voltage - Supply
3.3V, 5V
With Parallel Port
Yes
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3293-5
935277824112
SC28L201A1DGG
935277824112
SC28L201A1DGG
- Current page: 102 of 110
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Philips Semiconductors
9397 750 13138
Product data sheet
Fig 17. Transmitter timing
Fig 18. Receiver timing
(1) Timing shown for MR2[4] = 1.
(2) Timing shown for MR2[5] = 1.
(1) Timing shown for MR1[7] = 1.
(2) Shown for OPCR[4] = 1 and MR[6] = 0.
OVERRUN
transmitter
RXRDY/
(OP5)
receiver
enabled
RXRDY
FFULL
FFULL
RTS
CTSN
RTSN
enabled
(OP0)
(SR0)
(SR1)
(SR4)
TXRDY
RXD
RDN
(OP0)
(SR2)
WRN
(IP0)
TXD
(2)
(1)
(1)
(2)
OPR(0) = 1
D1
OPR[0] = 1
D8
D1
D1
status data
D1
D2
Rev. 01 — 31 October 2005
D2
D9
D8
break
start
D3
D11 will be lost
due to overrun
D9
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
D10
break
D10
break
status data
stop
D2
D11
D11 will not
be written to
the TxFIFO
D4
status data
D3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
D12, D13 will be lost
due to receiver disable
D12
OPR(0) = 1
status data
D12
D10
SC28L201
reset by command
002aab484
002aab485
D6
D13
102 of 110
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