SC28L201A1DGG,118 NXP Semiconductors, SC28L201A1DGG,118 Datasheet - Page 71
![IC UART W/FIFO 48-TSSOP](/photos/6/93/69378/48-tssop_sot370-1_pkg_sml.jpg)
SC28L201A1DGG,118
Manufacturer Part Number
SC28L201A1DGG,118
Description
IC UART W/FIFO 48-TSSOP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet
1.SC28L201A1DGG118.pdf
(110 pages)
Specifications of SC28L201A1DGG,118
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
256 Byte
Voltage - Supply
3.3V, 5V
With Parallel Port
Yes
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935277824118
SC28L201A1DGG-T
SC28L201A1DGG-T
SC28L201A1DGG-T
SC28L201A1DGG-T
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Philips Semiconductors
9397 750 13138
Product data sheet
8.5.4 Interrupt Vector Register (IVR)
8.5.5 Global Interrupting Channel Register (GICR)
8.5.6 Global Interrupting Byte Count Register (GIBCR)
Remark: The GIBCR, Global Interrupting Byte Count Register, may be read to determine
an exact character count.
The IVR contains the byte that will be placed on the data bus during an IACKN cycle when
the GCCR bits [2:1] are set to binary ‘01’. This is the unmodified form of the interrupt
vector.
Table 49:
A register associated with the interrupting channel as defined in the CIR. It contains the
channel number for the interrupting channel.
Table 50:
A register associated with the interrupting channel as defined in the CIR. Its numerical
value equals TxEL or RxFL at the time IACKN or ‘Update CIR’ command was issued. The
true number of bytes ready for transfer to the transmitter or transfer from the receiver. It is
undefined for other types of interrupts.
Table 51:
Bit
7:0
Bit
7:1
0
Bit
7:0
Else the interrupt is another type, specified in CIR[5:1].
Symbol
Symbol
Symbol
IVR - Interrupt Vector Register (address 0x64) bit description
GICR - Global Interrupting Channel Register (address 0x70) bit description
GIBCR - Global Interrupting Byte Count Register (address 0x71) bit description
Description
8 data bits of the Interrupt Vector (IVR)
Description
reserved
Channel code
Description
Channel byte count code
Rev. 01 — 31 October 2005
0 = a
1 = reserved
0000 0001 = 1
0000 0010 = 2
1111 1111 = 255
0000 0000 = 256
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC28L201
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