SC28L201A1DGG,118 NXP Semiconductors, SC28L201A1DGG,118 Datasheet - Page 30

• Manufacturer Part Number: SC28L201A1DGG,118
• Description: IC UART W/FIFO 48-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L201A1DGG,118

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935277824118; SC28L201A1DGG-T; SC28L201A1DGG-T

Philips Semiconductors
Table 4:
9397 750 13138
Product data sheet
Type
receiver without error
receiver with error
receiver watchdog
transmitter
change of break
Rx loopback error
change-of-state
Xon/Xoff
Counter/Timer
address recognition
no interrupt
threshold
Interrupt values
7.4.8.3 Interrupt arbitration and IRQN generation
Interrupt arbitration is the process used to determine that an interrupt request should be
presented to the host. The arbitration is carried out between the ‘Interrupt Threshold’ and
the ‘sources’ whose interrupt bidding is enabled by the IMR. The interrupt threshold is part
of the ICR (Interrupt Control Register) and is a value programmed by the user. The
‘sources’ present a value to the interrupt arbiter. That value is derived from four fields: the
channel number, type of interrupts source, FIFO fill level, and a programmable value. The
interrupt request (IRQN) will be asserted only when one or more of these values exceeds
the threshold value in the interrupt control register will.
Following assertion of the IRQN the host will either assert IACKN (Interrupt Acknowledge)
or will use the command to ‘Update the CIR’. At the time either action is taken the CIR will
capture the value of the source that is prevailing in the arbitration process. (Call this value
the winning bid.)
The SCLK drives the arbitration process. It evaluates the 12 bits of the arbitration bus at
1
values presented to the arbitration block during an arbitration cycle will be evaluated in the
next arbitration cycle.
For sources other than receiver and transmitters the user may set the high order bits of an
interrupt sources bid value, thus tailoring the relative priority of the interrupt sources. The
fill level of their respective FIFOs controls the priority of the receivers and transmitters.
The more filled spaces in the RxFIFO the higher the bid value; the more empty spaces in
the TxFIFO the higher its priority. Channels whose programmable high order bits are set
will be given interrupt priority higher than those with zeros in their high order bits, thus
allowing increased flexibility. The transmitter and receiver bid values contain the character
counts of the associated FIFOs as high order bits in the bid value. Thus, as a receivers
RxFIFO fills, it bids with a progressively higher priority for interrupt service. Similarly, as
empty space in a transmitters TxFIFO increases, its interrupt arbitration priority increases.
The programmable fields allow the software to adjust the authority or value of the bid for
those devices not having a FIFO.
Bit 11 to bit 4
RxFIFO filled Byte Count
RxFIFO filled Byte Count
RxFIFO filled Byte Count
TxFIFO empty Byte Count
programmed field
programmed field
programmed field
programmed field
programmed field
programmed field
0
bits 7:0 of Interrupt Control Register (ICR)
2
the SCLK rate developing a value for the CIR every two SCLK cycles. New arbitration
Rev. 01 — 31 October 2005
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
1
1
0
0
1
1
0
0
Bit 3
0
1
1
0
1
1
1
1
0
0
0
0
Bit 2
0
0
0
1
1
1
1
1
0
1
0
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Bit 1
1
1
0
0
0
1
0
1
0
1
0
0
SC28L201
Bit 0
channel number
channel number
channel number
channel number
channel number
channel number
Port 0 or 1
channel number
Counter 0 or 1
channel number
-
0
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