SC28L92A1B,557 NXP Semiconductors, SC28L92A1B,557 Datasheet - Page 30

• Manufacturer Part Number: SC28L92A1B,557
• Description: IC UART DUAL W/FIFO 44-PQFP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr
• Type: Dual UARTr

Specifications of SC28L92A1B,557

• Number Of Channels: 2, DUART
• Package / Case: 44-MQFP, 44-PQFP
• Features: False-start Bit Detection
• Fifo's: 16 Byte
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 0.2304 MBd
• Supply Voltage (max): 3.63 V or 5.5 V
• Supply Voltage (min): 2.97 V or 4.5 V
• Supply Current: 25 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1211; 935263294557; SC28L92A1B

NXP Semiconductors
SC28L92_7
Product data sheet
Table 30.
Bit
5
4
3 to 0
Symbol
-
-
-
MR2A - Mode Register 2 channel A (address 0x0) bit description
Rev. 07 — 19 December 2007
Description
Channel A transmitter Request To Send (RTS) control.
This bit controls the deactivation of the RTSAN output (OP0) by the
transmitter. This output is normally asserted by setting OPR[0] and
negated by resetting OPR[0]. MR2A[5] = 1 caused OPR[0] to be reset
automatically one bit time after the characters in the channel A transmit
shift register and in the Tx FIFO, if any, are completely transmitted
including the programmed number of stop bits, if the transmitter is not
enabled
This feature can be used to automatically terminate the transmission of a
message as follows (line turnaround):
Channel A transmitter Clear To Send (CTS) control.
If this bit is a 1, the transmitter checks the state of CTSAN (IP0) each time
it is ready to send a character. If IP0 is asserted (LOW), the character is
transmitted. If it is negated (HIGH), the TxDA output remains in the
marking state and the transmission is delayed until CTSAN goes LOW.
Changes in CTSAN while a character is being transmitted do not affect the
transmission of that character.
Stop bit length select. This field programs the length of the stop bit
appended to the transmitted character. Stop bit lengths of
1
lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1
stop bits can be programmed in increments of
receiver only checks for a mark condition at the center of the stop bit
position (one half-bit time after the last data bit, or after the parity bit if
enabled is sampled). Refer to
If an external 1 clock is used for the transmitter:
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
1. Program auto-reset mode: MR2A[5] = 1
2. Enable transmitter
3. Assert RTSAN: OPR[0] = 1
4. Send message
5. Disable transmitter after the last character is loaded into the channel A
6. The last character will be transmitted and OPR[0] will be reset one bit
0 = No RTS control
1 = RTS control
0 = Input CTSAN(IP0) has no effect on the transmitter
1 = CTS control enabled
MR2A[3] = 0 selects one stop bit
MR2A[3] = 1 selects two stop bits
9
Tx FIFO
time after the last stop bit, causing RTSAN to be negated
16
to 2 bits, in increments of
Table 32
1
16
bit, can be programmed for character
for the values.
1
16
bit. In all cases, the
SC28L92
© NXP B.V. 2007. All rights reserved.
…continued
9
16
to 1 and
1
16
to 2
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