DS3170N+ Maxim Integrated Products, DS3170N+ Datasheet - Page 43

• Manufacturer Part Number: DS3170N+
• Description: IC TXRX DS3/E3 100-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3170N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 120mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

Figure 8-16. DS3 Framed Mode Receive Serial Interface Pin Timing
Figure 8-17. E3 G.751 Framed Mode Receive Serial Interface Pin Timing
Figure 8-18. E3 G.832 Framed Mode Receive Serial Interface Pin Timing
8.3.4 Microprocessor Interface Functional Timing
8.3.4.1
NOTE: The transmit and receive order of the address and data bits are selected by the D[5]/SPI_SWAP pin. The
R/W (read/write) MSB bit and B (burst) LSB bit position is not effected by the D[5]/SPI_SWAP pin setting.
8.3.4.1.1
When CPHA = 0, CS may be de-asserted between accesses. An access is defined as one or two control bytes
followed by a data byte. CS cannot be de-asserted between the control bytes, or between the last control byte and
the data byte. When CPHA = 0, CS may also remain asserted between accesses. If it remains asserted and the
BURST bit is set, no additional control bytes are expected after the first control byte(s) and data are transferred. If
the BURST bit is set, the address will be incremented for each additional byte of data transferred until CS is de-
asserted. If CS remains asserted and the BURST bit is not set, a control byte(s) is expected following the data byte,
and the address for the next access will be received from that. Anytime CS is de-asserted, the BURST access is
terminated.
When CPHA = 1, CS may remain asserted for more than one access without being toggled high and then low
again between accesses. If the BURST bit is set, the address should increment and no additional control bytes are
DS3 RGCLK
E3 RGCLK
RCLKO or
RCLKO or
DS3 RSER
DS3 RDEN
E3 RGCLK
RCLKO or
E3 RSER
E3 RDEN
RSOFO
E3 RSER
E3 RDEN
RSOFO
RCLKI
RCLKI
RCLKI
RSOF
SPI Functional Timing Diagrams
SPI Transmission Format and CPHA Polarity
1
1
1
2
2
2
3
3
3
X1
4
4
4
5
5
5
6
6
FA1 11110110
6
FAS 1111010000
7
7
7
8
8
8
9
9
9
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10
10
10
11
11
11
12
12
12
13
13
13
FA2 00101000
A
14
14
14
15
15
N
15
DS3170 DS3/E3 Single-Chip Transceiver
16
17
18
19
20