DS3170N+ Maxim Integrated Products, DS3170N+ Datasheet - Page 4

• Manufacturer Part Number: DS3170N+
• Description: IC TXRX DS3/E3 100-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3170N+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 120mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

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10.11 BERT .................................................................................................................................................. 108
10.12 LIU – L
12.1 R
12.2 G
12.3 P
12.4 BERT .................................................................................................................................................. 144
12.5 B3ZS/HDB3 L
12.6 HDLC .................................................................................................................................................. 156
12.7 FEAC C
12.8 T
12.9 DS3/E3
13.1 JTAG D
13.2 JTAG TAP C
13.3 JTAG I
13.4 JTAG ID C
13.5 JTAG F
13.6 IO P
10.11.1 General Description ...................................................................................................................... 108
10.11.2 Features ....................................................................................................................................... 108
10.11.3 Configuration and Monitoring ........................................................................................................ 108
10.11.4 Receive Pattern Detection ............................................................................................................. 109
10.11.5 Transmit Pattern Generation ......................................................................................................... 111
10.12.1 General Description ...................................................................................................................... 112
10.12.2 Features ....................................................................................................................................... 112
10.12.3 Detailed Description ...................................................................................................................... 112
10.12.4 Transmitter ................................................................................................................................... 113
10.12.5 Receiver ....................................................................................................................................... 114
OVERALL REGISTER MAP
REGISTER MAPS AND DESCRIPTIONS
12.1.1 Global Register Bit Map ................................................................................................................ 119
12.1.2 HDLC Register Bit Map ................................................................................................................. 121
12.1.3 T3 Register Bit Map ...................................................................................................................... 123
12.1.4 E3 G.751 Register Bit Map ............................................................................................................ 124
12.1.5 E3 G.832 Register Bit Map ............................................................................................................ 125
12.2.1 Register Bit Descriptions ............................................................................................................... 126
12.3.1 Register Bit Descriptions ............................................................................................................... 133
12.4.1 BERT Register Map ...................................................................................................................... 144
12.4.2 BERT Register Bit Descriptions ..................................................................................................... 144
12.5.1 Transmit Side Line Encoder/Decoder Register Map ...................................................................... 151
12.5.2 Receive Side Line Encoder/Decoder Register Map ....................................................................... 152
12.6.1 HDLC Transmit Side Register Map................................................................................................ 156
12.6.2 HDLC Receive Side Register Map ................................................................................................ 159
12.7.1 FEAC Transmit Side Register Map ................................................................................................ 163
12.7.2 FEAC Receive Side Register Map ................................................................................................. 165
12.8.1 Trail Trace Transmit Side .............................................................................................................. 168
12.8.2 Trail Trace Receive Side Register Map ......................................................................................... 169
12.9.1 Transmit DS3 ................................................................................................................................ 174
12.9.2 Receive DS3 Register Map ........................................................................................................... 176
12.9.3 Transmit G.751 E3 ........................................................................................................................ 183
12.9.4 Receive G.751 E3 Register Map ................................................................................................... 186
12.9.5 Transmit G.832 E3 Register Map .................................................................................................. 191
12.9.6 Receive G.832 E3 Register Map ................................................................................................... 194
JTAG INFORMATION
PIN CONFIGURATIONS
DC ELECTRICAL CHARACTERISTICS
AC TIMING CHARACTERISTICS
RAIL
ORT
EGISTERS
LOBAL
INS
R
T
INE
NSTRUCTION
RACE
EGISTER
UNCTIONAL
ESCRIPTION
................................................................................................................................................ 207
R
ONTROLLER
FRAMER
EGISTERS
I
ODES
NTERFACE
B
......................................................................................................................................... 168
IT
ONTROLLER
INE
M
.................................................................................................................................... 133
................................................................................................................................... 174
................................................................................................................................... 206
APS
E
T
............................................................................................................................... 126
NCODER
............................................................................................................................... 202
R
.............................................................................................................................. 163
IMING
............................................................................................................................ 119
EGISTER AND
U
NIT
S
..................................................................................................................... 207
TATE
.................................................................................................................... 112
/D
ECODER
M
ACHINE
I
NSTRUCTIONS
................................................................................................... 151
D
ESCRIPTION
4 of 230
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DS3170 DS3/E3 Single-Chip Transceiver
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