DS3170N+ Maxim Integrated Products, DS3170N+ Datasheet - Page 169
![IC TXRX DS3/E3 100-CSBGA](/photos/6/94/69414/100-csbga_21-0153b_sml.jpg)
DS3170N+
Manufacturer Part Number
DS3170N+
Description
IC TXRX DS3/E3 100-CSBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3170.pdf
(230 pages)
Specifications of DS3170N+
Function
Single-Chip Transceiver
Interface
DS3, E3
Number Of Circuits
1
Voltage - Supply
3.135 V ~ 3.465 V
Current - Supply
120mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LBGA
Includes
DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 3 to 0: Transmit Trail Trace Identifier Address (TTIA[3:0]) – These four bits indicate the transmit trail trace
identifier byte to be read/written by the next memory access. Address 0h indicates the first byte of the transmit trail
trace identifier. Note: The value of these bits increments with each transmit trail trace identifier memory access
(when these bits are Fh, a memory access will return them to 0h).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 7 to 0: Transmit Trail Trace Identifier Data (TTD[7:0]) – These eight bits are the transmit trail trace identifier
data. The transmit trail trace identifier address will be incremented whenever these bits are read or written (when
address location Fh is read or written, the address will return to 0h).
12.8.2 Trail Trace Receive Side Register Map
The receive side utilizes seven registers.
Table 12-21. Trail Trace Receive Side Register Map
Address
0FCh
0FAh
0FEh
0F0h
0F2h
0F4h
0F6h
0F8h
TTD7
15
15
TT.RCR
TT.RTIAR
TT.RSR
TT.RSRL
TT.RSRIE
TT.RIR
TT.EIR
--
--
--
0
7
0
0
7
0
Register
--
TTD6
14
14
--
--
--
0
6
0
0
6
0
Trail Trace Receive Control Register
Trail Trace Receive Identifier Address Register
Trail Trace Receive Status Register
Trail Trace Receive Status Register Latched
Trail Trace Receive Status Register Interrupt Enable
Unused
Trail Trace Receive Identifier Register
Trail Trace Expected Identifier Register
Register Description
TT.TTIAR
Trail Trace Transmit Identifier Address Register
0EAh
TT.TIR
Trail Trace Transmit Identifier Register
0ECh
Reserved
TTD5
13
13
--
--
0
5
0
0
5
0
Reserved
169 of 230
TTD4
12
12
--
--
0
4
0
0
4
0
TTIA3
TTD3
11
11
--
--
0
3
0
0
3
0
DS3170 DS3/E3 Single-Chip Transceiver
TTIA2
TTD2
10
10
--
--
0
2
0
0
2
0
TTIA1
TTD1
--
--
9
0
1
0
9
0
1
0
TTIA0
TTD0
--
--
8
0
0
0
8
0
0
0
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