KMPC8548ECVTAUJC Freescale Semiconductor, KMPC8548ECVTAUJC Datasheet - Page 62

• Manufacturer Part Number: KMPC8548ECVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548ECVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

High-Speed Serial Interfaces (HSSI)
To illustrate these definitions using real values, consider the case of a CML (current mode logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD or
TD) is 500 mVp-p, which is referred as the single-ended swing for each signal. In this example, since the
differential signaling environment is fully symmetrical, the transmitter output’s differential swing (V
has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between
500 and –500 mV, in other words, V
differential voltage (V
15.2
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks inputs are SD_REF_CLK and
SD_REF_CLK for PCI Express and serial RapidIO.
The following sections describe the SerDes reference clock requirements and some application
information.
15.2.1
Figure 39
62
•
•
The supply voltage requirements for XV
SerDes Reference clock receiver reference circuit structure:
— The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the
A Volts
B Volts
SerDes Reference Clocks
shows a receiver reference diagram of the SerDes reference clocks.
in
termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling.
differential mode and single-ended mode description below for further detailed requirements.
SerDes Reference Clock Receiver Characteristics
Figure
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Figure 38. Differential Voltage Definitions for Transmitter or Receiver
SD_TX or
SD_RX
SD_TX or
SD_RX
39. Each differential clock input (SD_REF_CLK or SD_REF_CLK) has a 50-Ω
DIFFp
) is 500 mV. The peak-to-peak differential voltage (V
Differential Peak-Peak Voltage, V
OD
is 500 mV in one phase and –500 mV in the other phase. The peak
Differential Swing, V
Differential Peak Voltage, V
DD_SRDS2
ID
are specified in
DIFFpp
or V
OD
DIFFp
= 2*V
= A – B
= |A – B|
DIFFp
(not shown)
Table 1
DIFFp-p
and
V
Freescale Semiconductor
cm
Table
= (A + B)/2
) is 1000 mVp-p.
2.
OD
)