KMPC8548ECVTAUJC Freescale Semiconductor, KMPC8548ECVTAUJC Datasheet - Page 38

• Manufacturer Part Number: KMPC8548ECVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548ECVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Enhanced Three-Speed Ethernet (eTSEC)
Figure 18
8.2.7.2
38
TSECn_TX_CLK to RMII data TXD[1:0], TX_EN delay
Note:
1. The symbols used for timing specifications follow the pattern of t
TSECn_TX_CLK clock period
TSECn_TX_CLK duty cycle
TSECn_TX_CLK peak-to-peak jitter
Rise time TSECn_TX_CLK(20%–80%)
Fall time TSECn_TX_CLK (80%–20%)
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge
Note:
1. The symbols used for timing specifications follow the pattern of t
inputs and t
timing (MT) for the time t
the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.
For example, the subscript of t
used with the appropriate letter: R (rise) or F (fall).
inputs and t
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
going to the high (H) state or setup time. Also, t
signals (D) went invalid (X) relative to the t
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of t
with the appropriate letter: R (rise) or F (fall).
shows the RMII transmit AC timing diagram.
(first two letters of functional block)(reference)(state)(signal)(state)
TSECn_TX_CLK
(first two letters of functional block)(reference)(state)(signal)(state)
RMII Receive AC Timing Specifications
Parameter/Condition
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
TXD[1:0]
Parameter/Condition
TX_EN
TX_ER
Table 34. RMII Transmit AC Timing Specifications (continued)
MTX
MRX
clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,
MTX
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
Table 35. RMII Receive AC Timing Specifications
Figure 18. RMII Transmit AC Timing Diagram
represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is
t
RMTH
MRX
clock reference (K) going to the low (L) state or hold time. Note that, in general,
MRDXKL
t
RMT
symbolizes MII receive timing (GR) with respect to the time data input
Symbol
t
RMTDX
(first two letters of functional block)(signal)(state)(reference)(state)
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
t
t
for outputs. For example, t
RMTDX
RMTF
Symbol
t
t
t
t
t
RMRDV
RMRDX
1
t
t
RMRH
RMRR
RMRF
RMRJ
RMR
1
t
Min
RMTR
1.0
15.0
Min
1.0
1.0
4.0
2.0
35
—
MTKHDX
MRDVKH
Typ
—
20.0
Typ
50
—
—
—
—
—
MRX
Freescale Semiconductor
symbolizes MII transmit
symbolizes MII receive
clock reference (K)
Max
10.0
Max
25.0
250
2.0
2.0
65
—
—
Unit
Unit
ns
ns
ps
ns
ns
ns
ns
%
for
for