KMPC8548ECVTAUJC Freescale Semiconductor, KMPC8548ECVTAUJC Datasheet - Page 40

• Manufacturer Part Number: KMPC8548ECVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548ECVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

At recommended operating conditions with OV
Ethernet Management Interface Electrical Characteristics
9.2
Table 37
40
MDC frequency
MDC period
MDC clock pulse width high
MDC to MDIO valid
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
MDC fall time
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. This parameter is dependent on the eTSEC system clock speed, which is half of the Platform Frequency (f
4. Guaranteed by design.
5. t
Input high current (OV
Input low current (OV
Note:
1. Note that the symbol V
inputs and t
data timing (MD) for the time t
Also, t
(V) relative to the t
is used with the appropriate letter: R (rise) or F (fall).
ECn_MDC output clock frequency for a specific eTSEC port can be programmed by configuring the MgmtClk bit field of
MPC8548E’s MIIMCFG register, based on the platform (CCB) clock running for the device. The formula is: Platform Frequency
(CCB) ÷ (2 × Frequency Divider determined by MIICFG[MgmtClk] encoding selection). For example, if
MIICFG[MgmtClk] = 000 and the platform (CCB) is currently running at 533 MHz, f
8.3 MHz. That is, for a system running at a particular platform frequency (f
programmed between maximum f
MIIMCFG register section for more detail.3.The maximum ECn_MDC output clock frequency is defined based on the
maximum platform frequency for MPC8548E (533 MHz) divided by 64, while the minimum ECn_MDC output clock frequency
is defined based on the minimum platform frequency for MPC8548E (333 MHz) divided by 448, following the formula
described in Note 2 above.
CCB
is the platform (CCB) clock period.
MDDVKH
provides the MII management AC timing specifications.
MII Management AC Electrical Specifications
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter
symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
MDC
DD
DD
Table 36. MII Management DC Electrical Characteristics (continued)
= Max, V
clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention
= Max, V
IN
, in this case, represents the OV
Parameter
Table 37. MII Management AC Timing Specifications
MDC
IN
IN
= 0.5 V)
MDC
1
from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
= 2.1 V)
= f
DD
Symbol
t
t
t
t
MDKHDX
MDDXKH
MDKHDV
MDDVKH
t
t
t
CCB
f
t
MDCH
MDCR
MDHF
is 3.3 V ± 5%.
MDC
MDC
÷ 64 and minimum f
1
(16 × t
16 × t
IN
120.5
CCB
0.72
Min
32
symbol referenced in
—
—
5
0
CCB
× 8) – 3
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
MDC
Symbol
= f
I
I
IH
IL
CCB
CCB
Typ
2.5
—
—
—
—
—
—
—
÷ 448. Refer to MPC8572E reference manual’s
), the ECn_MDC output clock frequency can be
Table 1
MDC
(16 × t
–600
Min
= 533) ÷ (2 × 4 × 8) = 533) ÷ 64 =
—
and
MDKHDX
CCB
1389
Max
8.3
10
10
—
—
—
—
Table
× 8) + 3
symbolizes management
Freescale Semiconductor
2.
Max
40
—
CCB
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
). The actual
Notes
2, 3, 4
Unit
μA
μA
for
—
—
—
—
5
5
4
4