KMPC8548ECVTAUJC Freescale Semiconductor, KMPC8548ECVTAUJC Datasheet - Page 47

• Manufacturer Part Number: KMPC8548ECVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548ECVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Freescale Semiconductor
LA[27:31]/LBCTL/LBCKE/LOE/
Internal Launch/Capture Clock
LSDA10/LSDWE/LSDRAS/
Output (Address) Signal:
LSDCAS/LSDDQM[0:3]
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
LAD[0:31]/LDP[0:3]
Output Signals:
In PLL bypass mode, LCLK[n] is the inverted version of the internal clock
with the delay of
of the internal clock and are captured at falling edge of the internal clock
with the exception of LGTA/LUPWAIT (which is captured on the rising
edge of the internal clock).
Input Signals:
Input Signal:
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
LUPWAIT
LAD[0:31]
LCLK[n]
LGTA
LALE
Figure 24. Local Bus Signals (PLL Bypass Mode)
t
LBKHKT
. In this mode, signals are launched at the rising edge
t
LBKLOV1
t
LBKLOV2
NOTE
t
t
LBKLOV3
LBKLOV4
t
LBKHKT
t
LBIVKH1
t
LBOTOT
t
t
LBKLOX1
LBKLOX2
t
LBIXKH1
t
LBIVKL2
t
LBIXKL2
Local Bus
t
t
LBKLOZ1
LBKLOZ2
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