KMPC8548ECVTAUJC Freescale Semiconductor, KMPC8548ECVTAUJC Datasheet - Page 18

• Manufacturer Part Number: KMPC8548ECVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548ECVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

RESET Initialization
5
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8548E.
component(s).
Table 9
5.1
This section describes the AC electrical specifications for the power-on ramp rate requirements.
Controlling the maximum power-on ramp rate is required to avoid falsely triggering the ESD circuitry.
Table 10
18
Required ramp rate for MVREF
Required ramp rate for VDD
Note:
1. Maximum ramp rate from 200 to 500 mV is most critical as this range may falsely trigger the ESD circuitry.
2. VDD itself is not vulnerable to false ESD triggering; however, as per
Required assertion time of HRESET
Minimum assertion time for SRESET
PLL input setup time with stable SYSCLK before HRESET negation
Input setup time for POR configs (other than PLL config) with respect to
negation of HRESET
Input hold time for all POR configs (including PLL config) with respect to
negation of HRESET
Maximum valid-to-high impedance time for actively driven POR configs with
respect to negation of HRESET
Note:
1. SYSCLK is the primary clock input for the MPC8548E.
Core and platform PLL lock times
Local bus PLL lock time
PCI/PCI-X bus PLL lock time
recommended AVDD_CORE, AVDD_PLAT, AVDD_LBIU, AVDD_PCI1 and AVDD_PCI2 filters are all connected to VDD.
Their ramp rates should be equal to or less than the VDD ramp rate.
RESET Initialization
provides the PLL lock times.
provides the power supply ramp rate specifications.
Power-On Ramp Rate
Table 8
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
Parameter/Condition
provides the RESET initialization AC timing specifications for the DDR SDRAM
Parameter/Condition
Parameter
Table 8. RESET Initialization Timing Specifications
Table 10. Power Supply Ramp Rate
Table 9. PLL Lock Times
Section 21.2, “PLL Power Supply Filtering,”
Min
—
—
Min
100
100
—
3
4
2
Min
—
—
—
3500
4000
Max
Max
—
—
—
—
—
5
Freescale Semiconductor
Unit
V/s
V/s
Max
100
SYSCLKs
SYSCLKs
SYSCLKs
SYSCLKs
50
50
Unit
μs
μs
the
Notes
1, 2
Notes
Unit
1
μs
μs
μs
—
—
1
1
1
1