KMPC8548ECVTAUJC Freescale Semiconductor, KMPC8548ECVTAUJC Datasheet - Page 130

• Manufacturer Part Number: KMPC8548ECVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548ECVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

System Design Information
Note the following:
21.3
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8548E system, and the device
itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system
designer place at least one decoupling capacitor at each V
of the device. These decoupling capacitors should receive their power from separate V
OV
minimize inductance. Capacitors must be placed directly under the device using a standard escape pattern
as much as possible. If some caps are to be placed surrounding the part it should be routed with large trace
to minimize the inductance.
These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount technology) capacitors
should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V
smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating
to ensure the quick response time necessary. They should also be connected to the power and ground
planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS
tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor
for best values, types and quantity of bulk capacitors.
21.4
The SerDes block requires a clean, tightly regulated source of power (SV
jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is
outlined below.
Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections
from all capacitors to power and ground should be done with multiple vias to further reduce inductance.
130
DD
•
•
•
, GV
AV
Signals on the SerDes interface are fed from the XV
First, the board should have at least 10 × 10-nF SMT ceramic chip capacitors as close as possible
to the supply balls of the device. Where the board has blind vias, these capacitors should be placed
Decoupling Recommendations
SerDes Block Power Supply Decoupling Recommendations
DD
DD
_SRDS should be a filtered version of SV
DD
, LV
, TV
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
SV
DD
Note:
1. An 0805 sized capacitor is recommended for system initial bring-up.
DD
DD
, and GND power planes in the PCB, utilizing short low impedance traces to
, BV
DD
1.0 Ω
Figure 59. SerDes PLL Power Supply Filter
, OV
DD
, GV
2.2 µF
DD
1
, and LV
GND
2.2 µF
DD
DD
DD
.
, planes, to enable quick recharging of the
1
, TV
DD
power plane.
DD
0.003 µF
, BV
DD
DD
, OV
AV
and XV
DD
DD
_SRDS
, GV
Freescale Semiconductor
DD
DD
DD
) to ensure low
, TV
, and LV
DD
, BV
DD
DD
pin
,