KMPC8548ECVTAUJC Freescale Semiconductor, KMPC8548ECVTAUJC Datasheet - Page 27

• Manufacturer Part Number: KMPC8548ECVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548ECVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

8.2
The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI are presented in this
section.
8.2.1
The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI
specifications, since they have similar performances and are described in a source-synchronous fashion
like FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and
source clock in GMII fashion.
When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the
relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK,
while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit
clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out
onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is
intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a
source- synchronous timing reference. Typically, the clock edge that launched the data can be used, since
the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is
relationship between the maximum FIFO speed and the platform speed. For more information see
Section 4.5, “Platform to FIFO Restrictions.”
Freescale Semiconductor
Supply voltage 2.5 V
Output high voltage (LV
I
Output low voltage (LV
I
Input high voltage
Input low voltage
Input high current (V
Input low current (V
Notes:
1. LV
2. TV
3. Note that the symbol V
OH
OL
= 1.0 mA)
= –1.0 mA)
DD
DD
supports eTSECs 1 and 2.
supports eTSECs 3 and 4.
FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing
Specifications
FIFO AC Specifications
Table 23. GMII, MII, RMII, TBI, RGMII, RTBI, and FIFO DC Electrical Characteristics
Parameters
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
IN
IN
= GND)
DD
= LV
DD
/TV
IN
/TV
, in this case, represents the LV
DD
DD
DD
, V
= Min,
IN
= Min,
= TV
DD
)
LV
Symbol
DD
V
V
V
V
I
I
OH
IH
/TV
OL
IL
IH
IL
IN
and TV
DD
IN
GND –0.3
symbols referenced in
2.37
2.00
1.70
–0.3
Min
–15
—
LV
LV
Enhanced Three-Speed Ethernet (eTSEC)
DD
DD
/TV
/TV
0.40
Max
2.63
0.90
10
—
Table 1
DD
DD
+ 0.3
+ 0.3
and
Table
Unit
μA
μA
V
V
V
V
V
2.
1, 2, 3
Notes
1, 2
—
—
—
—
3
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