MD3331-D64-V3-X SanDisk, MD3331-D64-V3-X Datasheet - Page 60
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MD3331-D64-V3-X
Manufacturer Part Number
MD3331-D64-V3-X
Description
Manufacturer
SanDisk
Type
Flash Diskr
Datasheet
1.MD3331-D64-V3-X.pdf
(69 pages)
Specifications of MD3331-D64-V3-X
Density
64MByte
Operating Supply Voltage (typ)
3.3V
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Package Type
FBGA
Mounting
Surface Mount
Pin Count
69
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.5V
Operating Supply Voltage (max)
3.6V
Programmable
Yes
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MD3331-D64-V3-X
Manufacturer:
SANDISK
Quantity:
18 135
Company:
Part Number:
MD3331-D64-V3-X
Manufacturer:
TI
Quantity:
699
Part Number:
MD3331-D64-V3-X
Manufacturer:
M-SYSTEMS
Quantity:
20 000
10.4.2 Write Cycle Timing Standard Interface
Note: When designing your board to support also DiskOnChip Plus 32MB or 64MB devices, it is
60
Tsu (CE0)
Tho (CE0)
Tho (CE1)
Tsu (CE1)
Trec (WE)
Tw(WE)
Symbol
Tho (D)
T
Tho(A)
Tsu(D)
T
SU
WCYC
not possible to use VCC=2.5-3.6V, as these devices only support VCC=2.7-3.6V.
(A)
1.
2.
3.
4.
5.
6.
CE# may be asserted any time before or after OE# is asserted. If CE# is asserted after OE#, all timing relative to when OE# was
asserted will be referenced to the time CE# was asserted.
CE# may be negated any time before or after OE# is negated. If CE# is negated before OE#, all timing relative to when OE# was
negated will be referenced to the time CE# was negated.
The boot block is located at addresses 0000~07FFH and 1800H~1FFFH. Registers located at addresses 0800H~17FFH have a faster
access time than the boot block. Access to the boot block is not required after the boot process has completed.
Systems that do not access the boot block may implement only the read access timing for “all other registers”. This will increase the
systems performance, however it will prevent access to the boot block.
Add 260 ns on the first read cycle when exiting Power-Down mode. See Section 5.3 for more information.
No load (C
A[12:0], BHE#
Address to WE#
WE#
WE# asserted width
Write Cycle Time
CE#
WE#
OE# or WE#
CE#
WE#
D to WE#
WE#
Table 16: Standard Interface Write Cycle Parameters (VCC=2.5-3.6V)
D[15:0]
L
= 0 pF).
WE#
CE#
OE#
to WE#
to WE#
to Address hold time
to CE#
to start of next cycle
to D hold time
setup time
Description
Figure 21: Standard Interface Write Cycle Timing
T
HO
to CE#
(CE1
setup time
hold time
or OE#
T
setup time
SU
(A)
T
SU
hold time
2
(CE0)
1
setup time
Data Sheet, Rev. 1.8
T
HO
(A)
Tw(WE)
VCC=2.5-3.6V
Min
28
20
50
83
29
VCCQ=VCC
-2
--
--
6
6
0
t
SU
tT
(D)
WCYC
T
HO
(CE0)
Max
T
T
HO
REC
(D)
T
Mobile DiskOnChip Plus 16/32MByte
VCCQ=1.65-1.9V
(WE)
SU
VCC=2.5-3.6V
Min
28
49
83
20
29
(CE1
-2
--
--
6
6
0
Max
95-SR-000-10-8L
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns