MD3331-D64-V3-X SanDisk, MD3331-D64-V3-X Datasheet - Page 49

• Manufacturer Part Number: MD3331-D64-V3-X
• Manufacturer: SanDisk
• Type: Flash Diskr

Specifications of MD3331-D64-V3-X

• Density: 64MByte
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Package Type: FBGA
• Mounting: Surface Mount
• Pin Count: 69
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 3.6V
• Programmable: Yes
• Lead Free Status / Rohs Status: Not Compliant

2.
3.
4.
Stage 2
Configure the software so that for every long flash I/O operation, the following steps occur:
1.
2.
3.
4.
For further information on implementing the interrupt mechanism, please refer to application note
AP-DOC-063, Improving the Performance of DiskOnChip Plus Devices Using the IRQ# Pin.
9.5
The following section describes hardware design issues.
9.5.1
Wait states can be implemented only when Mobile DiskOnChip Plus is designed in a bus that
supports a Wait state insertion, and supplies a WAIT signal.
9.5.2
Power PC, ARM, and other RISC processors can use either Big or Little Endian systems. Mobile
DiskOnChip Plus uses the Little Endian system. Therefore, bytes D[7:0] are its Least Significant
Byte (LSB) and bytes D[15:8] are its Most Significant Byte (MSB). Within the bytes, bit D0 and bit
D8 are the least significant bits of their respective byte. When connecting Mobile DiskOnChip Plus
to a device that supports the Big Endian system, make sure to that the bytes of the CPU and Mobile
DiskOnChip Plus match.
Note: Processors like the Power PC also change the bit ordering within the bytes. Failing to follow
For further information on how to connect Mobile DiskOnChip Plus to support CPUs that use the
Big Endian system, refer to the application note for the relevant CPU.
49
o
Note: Refer to Section 7.10 for further information on the value to be written to this register.
The host interrupt is configured to the selected input sensitivity, either edge or level.
The handshake mechanism between the interrupt handler and the OS is initialized.
The interrupt service routine to the host interrupt is connected and enabled.
The correct value is written to the Interrupt Control register to enable the IRQ# interrupt.
Note: Refer to Section 7.10 for further information on the value to be written to this register.
The flash I/O operation starts.
Control is returned to the OS to continue other tasks. When the IRQ# interrupt is received,
other interrupts are disabled and the OS is flagged.
The OS either returns control immediately to the TrueFFS driver, or waits for the appropriate
condition to return control to the TrueFFS driver.
these rules results in improper connection of Mobile DiskOnChip Plus and prevents the
TrueFFS driver from identifying Mobile DiskOnChip Plus.
Platform-Specific Issues
Wait State
Big and Little Endian Systems
Output sensitivity: Either edge or level triggered
Data Sheet, Rev. 1.8
Mobile DiskOnChip Plus 16/32MByte
95-SR-000-10-8L