DA82562EM Intel, DA82562EM Datasheet - Page 93

• Manufacturer Part Number: DA82562EM
• Manufacturer: Intel

Specifications of DA82562EM

• Lead Free Status / Rohs Status: Not Compliant

6.4.2.5.2
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Transmit Command Operation
The execution of a transmit command causes frame transmission. If the frame experiences
collisions, the device automatically attempts to re-transmit the frame up to 15 times. If it still
experiences collisions after 16 tries, the device increments the maximum collisions counter. The
following sequence outlines a general transmit command operation for the flexible memory
structure (TCBs and TBDs).
The flow of events for transmitting a single frame using a flexible TCB is:
The transmit command differs from other action commands. Generally, the action commands have
parameters in one memory block. However, the transmit command may have parts of the
parameters scattered in a linked list of buffers. The CU spontaneously pre-fetches the buffers in the
list.
10. After the last buffer is completely read, the device sets the C bit in the TCB, enabling the
11. The device completes the frame transmission to the serial interface (for the 82557, either MII
12. The controller updates its internal transmit status counters.
5. Fetch data if the transmit buffer pointer is zero (invalid) in the second TBD or poll the TBD.
6. Finish the transmission if the EL bit is set.
1. Place the transmit command opcode (100b) in the command word.
2. Place the destination address and length field in the appropriate transmit structure.
3. Configure the transmit buffer address and size (actual count) for each buffer. The last buffer in
1. The CPU creates a TCB and TBD array in system memory. The transmit buffer address
2. The CPU writes a CU start command (or CU resume if the CU is suspended) into the SCB.
3. The device processes the SCB, reads the SCB general pointer, and clears the SCB command
4. The device reads the first TCB in the CBL and the first TBD from the TBD array.
5. If the TCB size field does not equal zero, the TCB holds data to be transmitted and the device
6. The controller reads the first transmit data buffer from host memory at the address provided in
7. After the transmit threshold bytes are read (either from one or multiple transmit buffers), the
8. If there are multiple TBDs, the controller reads the next TBD from the TBD array.
9. After the first buffer has been completely read, the device starts reading the transmit data from
The TBD array address should point to the first TBD in the array. When the simplified
memory structure is used, the TBD array address is not used.
the TBD array is determined by the TBD number field in the TCB.
pointers in the TBDs point to valid data buffers in host memory.
The write event causes the device to read the CUC field, and the device notices that it should
start the CU.
word.
reads this data first.
the transmit buffer #0 address field of the transmit buffer array.
controller begins frame transmission to the PHY interface.
the next buffer.
driver to re-use reuse the TCB, TBDs, and transmit buffers. The controller posts the underrun
bit in the TCB if an underrun occurred since the last TCB status was reported.
or 82503).
Host Software Interface
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