DA82562EM Intel, DA82562EM Datasheet - Page 121

• Manufacturer Part Number: DA82562EM
• Manufacturer: Intel

Specifications of DA82562EM

• Lead Free Status / Rohs Status: Not Compliant

6.6.3
6.6.3.1
6.6.3.2
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Table 55. Flow Control Configuration Bits
Note: The 82558 and 82559 do not transmit pause low frames.
Priority Aware Frame Based Flow Control
The 82558 and later generation controllers have the ability to respond to priority aware frame
based flow control frames. Their operation relates to multiple queues.
Priority Flow Control Operation
The 82558 and later generation controllers can receive two types of flow control frames:
When the device receives a pause frame, it stops all transmission at the CSMA level as defined in
IEEE draft standard 802.3x.
When the controller receives a pause low frame, it stops transmitting the LPQ at the micromachine
level. When a pause low flow control frame is received, the device continues to transmit all frames
in its transmit FIFO. When the device is used with priority aware FC it is recommended that the
two frames in FIFO configuration bit is set so that the number of frames is no more than two.
When the device receives a flow control frame (either a pause frame or a pause low frame), this
frame overrides any flow control frame previously received. If the device was paused due to a
pause frame and it receives a pause low frame, it starts transmitting high priority frames (and any
low priority packets that were in the transmit FIFO). If the device was paused low due to a pause
low frame and it receives a pause frame, it stops transmitting high priority frames immediately.
The pause and pause low frames do not affect the device’s CU state (as reflected in the CUS field
in the SCB).
Flow Control Frame Format
The pause and pause low flow control frames share the same frame format.
illustrates a flow control frame.
Transmit FC
Receive FC
ReStart
Receive FC
ReStop
Reject FC
FC Delay
•
•
Name
Pause. The normal IEEE pause frames that stop all transmission (as discussed above).
Pause Low. This is a new low priority pause frame that stops only the low priority queue
(LPQ).
Byte 19, bit 2
Byte 19, bit 4
Byte 19, bit 3
Byte 19, bit 5
Byte 16, bits 7:0 (LSB)
Byte 17, bits 7:0 (MSB)
Configuration Byte
Map Location
IEEE frame based transmit flow control.
IEEE frame based receive flow control - ReStart mode. 0 (off)
IEEE frame based receive flow control - ReStop mode. 0 (off)
When this bit is set, FC frames will not be passed to
the receive FIFO like regular frames.
This is the slot time delay number used for the time
parameter in the assembly of pause frames (for
pausing the other node transmissions).
Description
Host Software Interface
Table 54 on page 110
0 (on)
0 (off)
4000h
Default
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