DA82562EM Intel, DA82562EM Datasheet - Page 62

• Manufacturer Part Number: DA82562EM
• Manufacturer: Intel

Specifications of DA82562EM

• Lead Free Status / Rohs Status: Not Compliant

Host Software Interface
6.3.9
54
Table 29. Flow Control Threshold Values
Table 30. Power Management Driver Register Location
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Power Management Driver Register
The Power Management Driver Register (PMDR) provides an indication of power management
events. It is an 8-bit field located at offset 18h of the CSR. This register is only present in the 82558
and later generation controllers and is not valid on the 82557.
The PMDR has evolved over time in the various Intel Fast Ethernet controllers. The PMDR bits for
the 82558 and 82559 are described below.
000
001
010
011
100
101
110
111
•
FC TH Value
Bits 10:8 - FC Threshold. The 82558 or later generation controller is capable of generating a
flow control pause frame when its receive FIFO is almost full. This three-bit field determines
the number of bytes left in the receive FIFO when the pause frame is generated. The trade-off
occurs between a higher degree of data integrity (high flow control threshold value) or high
performance (low flow control threshold value).
PMDR
EEPROM Control Register
Upper Word (D31:D16)
SCB Command Word
Early Receive Interrupt Receive Byte Count Register
0.5 Kbyte
1 Kbyte
1.25 Kbyte
1.5 Kbyte
1.75 Kbyte
2 Kbyte
2.25 Kbyte
2.5 Kbyte
FC TH (free bytes
in receive FIFO)
FC Xon/Xoff
SCB General Pointer
MDI Control Register
PORT
Fast system (recommended default).
Slow system.
SCB Status Word
FC Threshold
Lower Word (D15:D0)
Comment
Reserved
Early Rx Int
Base + 10h
Base + 14h
Base + 18h
Base + 0h
Base + 4h
Base + 8h
Base + Ch
Offset