DA82562EM Intel, DA82562EM Datasheet - Page 106

• Manufacturer Part Number: DA82562EM
• Manufacturer: Intel

Specifications of DA82562EM

• Lead Free Status / Rohs Status: Not Compliant

Host Software Interface
6.4.3.1.2
98
Figure 24. Simplified Memory Structure
Figure 25. Receive Frame Descriptor Format
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Receive Frame Descriptor Format
00h
04h
08h
0Ch
EL (Bit 31)
S (Bit 30)
H (Bit 20)
SF (Bit 19)
C (Bit 15)
OK (Bit 13)
Status Bits
(Bits 12:0)
Offset
SCB
EL
Link Address (A31:A0)
Reserved
0
S
0
The EL bit indicates that this RFD is the last one in the RFA.
The S bit suspends the RU after receiving the frame.
The H bit indicates if the current RFD is a header RFD. If it equals 1, the current RFD is
a header RFD, and if it is 0, it is not a header RFD.
NOTE: If a load HDS command was not previously issued, the device disregards this
The SF bit equals 0 for simplified mode.
This bit indicates the completion of frame reception. It is set by the device.
The OK bit indicates whether the frame was received without any errors and stored in
memory. If the last frame was received with sufficient memory space, the OK bit will be
set, even if it was the last RFD in the RFA with the EL bit set. After receiving the frame,
the device enters the no resource condition, generates an RNR interrupt, and starts
discarding frames until the RU is restarted with sufficient resources.
This field contains the results of the receive operation:
Command Word Bits 31:16
000000000
Size
Sequential
Data Buffer
RFD
bit.
H
RECEIVE FRAME AREA
SF
Sequential
Data Buffer
RFD
000
C
EOF
Sequential
Data Buffer
RFD
0
F
OK
Actual Count
Status Word Bits 15:0
Sequential
Data Buffer
Status Bits
RFD