DA82562EM Intel, DA82562EM Datasheet - Page 58

• Manufacturer Part Number: DA82562EM
• Manufacturer: Intel

Specifications of DA82562EM

• Lead Free Status / Rohs Status: Not Compliant

Host Software Interface
6.3.5.2
6.3.5.3
50
Table 25. MDI Control Register Bits
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
MDI Write cycle
The sequence of events for a MDI write cycle is:
MDI Read cycle
The sequence of events for a MDI read cycle is:
Bits
31:30
29
28
27:26
25:21
20:16
15:0
1. The CPU performs a PCI write cycle to the MDI register with:
2. The LAN controller shifts the following sequence out of the MDIO pin:
3. The LAN controller asserts an interrupt indicating MDI is finished if the Interrupt Enable bit
4. The LAN Controller sets the Ready bit in the MDI register to indicate step 2 has been
5. The CPU may issue a new MDI command.
1. The CPU performs a PCI write cycle to the MDI register with:
was set.
completed.
a. Ready (bit 28) = 0
b. Interrupt Enable (bit 29) = 1 or 0
c. Opcode (bits 27:26) = 01b (write)
d. PHYAdd = the PHY address from the MDI register
e. RegAdd = the register address of the specific register to be accessed (0 through 31)
a. Ready (bit 28) = 0
b. Interrupt Enable (bit 29) = 1 or 0
c. Opcode (bits 27:26) = 10b (read)
f. Data = data to be written to the specified PHY register
<PREAMBLE><01><01><PHYADD><REGADD><10><DATA><IDLE>
Field
Reserved
IE
R
Opcode
PHYAdd
RegAdd
Data
Description
Reserved. This field is reserved and returns 0.
Interrupt Enable. When this bit is set to 1 by software, it causes the device to assert
an interrupt indicating the end of an MDI cycle.
Ready. set to 1 by the device at the end of MDI transaction (i.e., indicates a Read or
Write has been completed. It should be reset to 0 by software at the same time the
command is written.
Opcode. For an MDI write, the opcode equals 01b, and for MDI read, 10b. 00b and
11b are reserved and should not be used.
PHY Address.
PHY Register Address.
NOTE: This value equals 1 for Intel PRO/100B TX and T4 adapters.
Data. In a write command, software places the data bits here and the device shifts
them out to the PHY. In a read command the device reads these bits serially from the
PHY and software can read them from this location.