DA82562EM Intel, DA82562EM Datasheet - Page 145

• Manufacturer Part Number: DA82562EM
• Manufacturer: Intel

Specifications of DA82562EM

• Lead Free Status / Rohs Status: Not Compliant

Wake-up Functionality
A.1
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Note: This appendix applies only to the 82558 and subsequent devices.
Wake-up Capability
Wake-up functionality was first introduced with the 82558 A-step. This component is capable of
being brought out of a power managed stated by programming it to wake on reception of a packet
addressed to it, a multicast or broadcast packet, any received packet, or a Magic Packet*. These
wake-up capabilities are enabled through the Configuration Command bits.
This functionality was carried forward to the 82558 B-step and all subsequent Fast Ethernet
devices. However, the wake on reception of a broadcast packet was changed to wake on reception
of broadcasted ARP or VLAN ARP. The Configuration Command bits used to enable these wake-
up capabilities were also modified from the 82558 A-step. In addition, the 82558 B-step and all
subsequent silicon also support the ability to wake on link status change.
If the device is enabled, it notifies the system of a wake-up packet event by asserting the PME# pin.
The PME enable bit is located in the PMCSR. It is system responsibility to ensure that this bit is set
only when the device is in the D1, D2, or D3 states (as required by the PCI Power Management
Specification). After a wake-up event, the PME status bits in the PMCSR and CSR are set
regardless of the value of the PME enable bit.
There are two types of wake-up events: reception of a wake-up packet and a link status event. The
detection mechanism for wake-up packets (packet filtering) is further categorized by fixed packet
filtering implemented by the hardware in the CSMA unit and flexible packet filtering implemented
by the loadable microcode.
The device uses three different mechanisms to wake the system up:
The device is able to detect fixed packet and link status wake-up events to the system if power is
supplied to the device. This may be the main PC power supply or an auxiliary power supply that is
active whenever the system is plugged in.
The ability to use loadable microcode for flexible frame filtering requires a valid clock on the PCI
CLK pin. This may be the CLK signal from the PCI bus or other valid clock signal connected to the
device clock pin while the system is in low power mode.
The following table describes wake-up capabilities in different combinations of power supply and
clock:
1. Fixed packet wake up. This is implemented in hardware using the clock driven on the X1 pin.
2. Flexible packet filtering. This is implemented in the loadable microcode using the PCI CLK
3. Link status change event.
pin as clock. (The discussion of microcode is beyond the scope of this document.)
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