DA82562EM Intel, DA82562EM Datasheet - Page 21

• Manufacturer Part Number: DA82562EM
• Manufacturer: Intel

Specifications of DA82562EM

• Lead Free Status / Rohs Status: Not Compliant

4.1.5
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Figure 3. Command Register
Table 2.
Revision (Offset 8)
This register specifies a device specific revision identifier. For the 82557 C-Step, 82558, and
82559, this field may be automatically loaded from the EEPROM at power on or upon the assertion
of a PCI reset. The default revision register values for the various devices are:
Device and Revision ID
15
Status Bits
15
14
13
12
11
10:9
8
7
6
5
4
3:0
82557 A-Step
82557 B-Step
82557 C-Step
82558 A-Step
82558 B-Step
82559 A-Step
82559 B-Step
82559 C-Step
Bits
1 (82559
(82557)
82558)
Initial
Value
Device
and
01
x
x
x
x
0
x
1
0
0
0
0
Detected parity error.
Signaled system error.
Received master abort.
Received target abort.
Signaled target abort.
DEVSEL timing (indicates minimum timing).
Data parity reported.
Fast back-to-back capable.
UDF supported.
66 MHz capable.
Capabilities list. This bit indicates whether the device implements a list of new capabilities
such as PCI Power Management. If it is set, the Cap_Ptr register in the PCI Configuration
Space points to the location of the first item in the Capabilities List.
NOTE: This bit is set to 1 for the 82559 and 82558 if it is not disabled by the EEPROM. It
Reserved.
is always equal to 0 for the 82557.
01h
02h
03h
04h
05h
06h
07h
08h
Revision ID
2.0
2.0
2.1
2.1
2.1
2.1
2.1
2.2
PCI Revision
Supported
Description
Yes
Yes
No
Yes
Yes
No
No
Yes
Intel Driver
Supported
4
3
Reserved
PCI Interface
13
0