KM29W040AT Samsung Semiconductor, KM29W040AT Datasheet - Page 5

• Manufacturer Part Number: KM29W040AT
• Manufacturer: Samsung Semiconductor

Specifications of KM29W040AT

• Cell Type: NAND
• Density: 4Mb
• Access Time (max): 15us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 8b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-II
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

PIN DESCRIPTION
Command Latch Enable(CLE)
Address Latch Enable(ALE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
The ALE input controls the path activation for address and input data to the internal address/data register. Addresses are latched on
the rising edge of WE with ALE high, and input data is latched when ALE is low.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Read Enable(RE)
Write Protect(WP)
KM29W040AT, KM29W040AIT
Write Enable(WE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid t
of RE which also increments the internal column address counter by one.
I/O Port : I/O
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
0
~ I/O
7
5
FLASH MEMORY
REA
after the falling edge