KM29W040AT Samsung Semiconductor, KM29W040AT Datasheet - Page 19

• Manufacturer Part Number: KM29W040AT
• Manufacturer: Samsung Semiconductor

Specifications of KM29W040AT

• Cell Type: NAND
• Density: 4Mb
• Access Time (max): 15us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 8b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-II
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

BLOCK ERASE
The Erase operation is done 4K Bytes(1 block) at a time. Block address loading is accomplished in two cycles initiated by an Erase
Setup command(60H). Only address A
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase, erase-verify and pulse
repetition where required.
Figure 6. Block Erase Operation
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is complete, and whether
the program or erase operation completed successfully. After writing 70H command to the command register, a read cycle outputs
the contents of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, the required read command(00H) should be input before serial page read cycle.
R/B
I/O
Table2. Status Register Definition
KM29W040AT, KM29W040AIT
0
~
7
I/O2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SR
0
1
3
4
5
6
7
60H
Address Input(2Cycle)
Block Add. : A
12
to A
18
Reserved for Future Use
8
are valid while A
~A
Device Operation
18
Write Protect
Program
Status
D0H
8
19
to A
11
is ignored. The Erase Confirm command(D0H) following the
t
BERS
"0" : Successful Program
"1" : Error in Program
"0"
"0"
"0"
"0"
"0"
"0"
"0" : Busy
"0" : Protected
FLASH MEMORY
Definition
"1" : Not Protected
"1" : Ready