KM29W040AT Samsung Semiconductor, KM29W040AT Datasheet
KM29W040AT
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KM29W040AT Summary of contents
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... KM29W040AT, KM29W040AIT Document Title 512K x 8 bit NAND Flash Memory Revision History Revision No. History 0.0 Initial issue. 1.0 1) Changed Operating Voltage 2.7V ~ 5.5V 1.1 Data Sheet 1999 1) Added CE don’ t care mode during the data-loading and reading The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications ...
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... KM29W040AT, KM29W040AIT 512K x 8 Bit NAND Flash Memory FEATURES Voltage Supply: 3.0V~5.5V Organization - Memory Cell Array : 512K Data Register : bit Automatic Program and Erase (Typical) - Frame Program : 32 Byte in 500 s - Block Erase : 4K Byte in 6ms 32-Byte Frame Read Operation - Random Access : 15 s(Max.) - Serial Frame Access : 120ns(Min.) ...
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... KM29W040AT, KM29W040AIT Figure 1. FUNCTIONAL BLOCK DIAGRAM Command Figure 2. ARRAY ORGANIZATION The 1st Block (4KB Row 1 2 (=128 Blocks) 128Byte Column Frame Register 32 Byte I/O I 1st Cycle 2nd Cycle 3rd Cycle NOTE : *( can X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command ...
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... KM29W040AT, KM29W040AIT PRODUCT INTRODUCTION The KM29W040A bit memory organized as 4096 rows by 1024 columns. A 256-bit data register is connected to memory cell arrays accommodating data transfer between the registers and the cell array during frame read and frame program operations. The memory array is composed of unit NAND structures in which 8 cells are connected serially. ...
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... KM29W040AT, KM29W040AIT PIN DESCRIPTION Command Latch Enable(CLE) The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. Address Latch Enable(ALE) The ALE input controls the path activation for address and input data to the internal address/data register ...
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... Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND, KM29W040AT Parameter Supply Voltage ...
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... KM29W040AT, KM29W040AIT VALID BLOCK Parameter Valid Block Number NOTE : 1. The KM29W040A may include invalid blocks. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid blocks for program and erase. During its lifetime of 10 years and/or 100K program/erase cycles,the minimum number of valid blocks are guaranteed though its initial number could be reduced ...
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... KM29W040AT, KM29W040AIT AC Timing Characteristics for Command / Address / Data Input Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Set-up Time Data Hold Time Write Cycle Time WE High Hold Time AC Characteristics for Operation ...
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... KM29W040AT, KM29W040AIT NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. Typically, an invalid block will contain a single bad bit. The information regarding the invalid block( called as the invalid block informa- tion ...
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... KM29W040AT, KM29W040AIT KM29W040A Technical Notes(Continued) Error in program or erase operation The device may fail during a program or erase operation. The following possible failure modes should be considered when implementing a highly reliable system. Failure Mode Block Erase Failure Frame Program Failure Program Failure Single Bit (" ...
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... KM29W040AT, KM29W040AIT System Interface Using CE don’ t -care. For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 32byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read- ing would provide significant savings in power consumption ...
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... KM29W040AT, KM29W040AIT * Command Latch Cycle CLE CE WE ALE I Address Latch Cycle CLE CE WE ALE I CLS CLH ALS ALH Command t CLS ALS FLASH MEMORY ALH ...
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... KM29W040AT, KM29W040AIT * Input Data Latch Cycle CLE CE t ALS ALE Burst Read Cycle After Frame Access R/B NOTES : Transition is measured 200mV from steady state voltage with load DIN 0 DIN 1 (CLE=L, WE=H, ALE= REH REA REA Dout Dout This parameter is sampled and not 100% tested. ...
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... KM29W040AT, KM29W040AIT * Status Read Cycle CLE I READ OPERATION (READ ONE FRAME) CLE CE WE ALE 00h I Column Address R/B t CLS t CLH t REA WHR 70H Dout N Dout N Row Address Busy 14 FLASH MEMORY t CSTO t CHZ t t RSTO RHZ t IR Status Output t RC Dout N+2 ...
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... KM29W040AT, KM29W040AIT READ OPERATION (INTERCEPTED BY CE) CLE CE WE ALE 00h I Column Address R/B PROGRAM OPERATION CLE ALE RE I/O ~ 80H Sequential Data Column Input Command Address R Dout Row Address Busy t WC Din Din N Byte Data Row Serial Input Address 15 FLASH MEMORY t CHZ ...
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... KM29W040AT, KM29W040AIT BLOCK ERASE OPERATION CLE CE WE ALE RE I/O ~ 60H Block Address R/B Auto Block Erase Setup Command DOH 16 18 Busy Erase Command 16 FLASH MEMORY t BERS ...
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... KM29W040AT, KM29W040AIT DEVICE OPERATION FRAME READ Upon initial device power up or after excution of Reset(FFh) command, the device defaults to Read mode. This operation is also ini- tiated by writing 00H to the command register along with three address cycles. The three cycle address input must be given for access to each new frame ...
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... KM29W040AT, KM29W040AIT FRAME PROGRAM The device is programmed on a frame basis. The addressing may be done in random order in a block. A frame program cycle consist of a serial data loading period in which bytes of data must be loaded into the device, and a nonvolatile programming period in which the loaded data is programmed into the appropriate cells. ...
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... KM29W040AT, KM29W040AIT BLOCK ERASE The Erase operation is done 4K Bytes(1 block time. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60H). Only address A block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. ...
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... KM29W040AT, KM29W040AIT RESET The device offers a reset feature, executed by writing FFH to the command register. When the device is in Busy state during the read, program or erase mode, the reset operation will abort these operation. In the case of Reset during Program or Erase opera- tions, the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The device enters the Read mode after completion of Reset operation as shown Table 3 ...
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... KM29W040AT, KM29W040AIT DATA PROTECTTION The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at V during power-up and power-down as shown in Figure 8. The two step command sequence for program/erase provides additional software protection ...
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... KM29W040AT, KM29W040AIT PACKAGE DIMENSIONS 44(40) LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II) 44(40) - TSOP2 - 400F #44(40) #1 18.81 0.741 18.41 0.10 0.725 0.004 0.805 0.35 0.10 0.032 0.014 0.004 #23(21) #22(20) Max. 0.80 0.0315 22 FLASH MEMORY Unit :mm/Inch 0~8 0.25 0.010 TYP ...