KM29W040AT Samsung Semiconductor, KM29W040AT Datasheet - Page 17

• Manufacturer Part Number: KM29W040AT
• Manufacturer: Samsung Semiconductor

Specifications of KM29W040AT

• Cell Type: NAND
• Density: 4Mb
• Access Time (max): 15us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 8b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-II
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

DEVICE OPERATION
FRAME READ
Upon initial device power up or after excution of Reset(FFh) command, the device defaults to Read mode. This operation is also ini-
tiated by writing 00H to the command register along with three address cycles. The three cycle address input must be given for
access to each new frame.
The read mode is enabled when the frame address is changed. 32 bytes of data within the selected frame are transferred to the data
registers in less than 15 s(t
the data in a frame is loaded into the registers, they may be read out in 120ns cycle time by sequentially pulsing RE with CE staying
low. High to low transitions of the RE clock output the data starting from the selected column address up to the last column address
within the frame(column 32).
KM29W040AT, KM29W040AIT
Figure 3. Read Operation
CLE
CE
WE
ALE
RE
R/B
I/O
0
~
7
00H
R
A
). The CPU can detect the completion of this data transfer(t
0
Start Add.(3Cycle)
~A
7
& A
8
~A
18
Busy(Seek Time)
0
Seek Time
31
17
R
) by analyzing the output of R/B pin. Once
Data Output(Sequential)
FLASH MEMORY