KM29W040AT Samsung Semiconductor, KM29W040AT Datasheet - Page 18

• Manufacturer Part Number: KM29W040AT
• Manufacturer: Samsung Semiconductor

Specifications of KM29W040AT

• Cell Type: NAND
• Density: 4Mb
• Access Time (max): 15us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 8b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-II
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 20mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

Figure 5. Example of Dividing a Frame into 10 Partial Program Units
FRAME PROGRAM
The device is programmed on a frame basis. The addressing may be done in random order in a block. A frame program cycle consist
of a serial data loading period in which up to 32 bytes of data must be loaded into the device, and a nonvolatile programming period
in which the loaded data is programmed into the appropriate cells.
The sequential data loading period begins by inputting the frame program setup command(80H), followed by the three cycle address
input and then sequential data loading. The bytes other than those to be programmed do not need to be loaded.
The frame Program confirm command(10H) initiates the programming process. Writing 10H alone without previously entering the
serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings
necessary for program and verify, thereby freeing the CPU for other tasks. The CPU can detect the completion of a program cycle by
monitoring the R/B output, or the Status bit(I/O
valid while programming is in progress. When the frame Program is complete, the Write Status Bit(I/O
nal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Sta-
tus command mode until another valid command is written to the command register.
FRAME PROGRAM
Figure 4. Frame Program Operation
While the frame size of the device is 32 Bytes, not all the bytes in a frame have to be programmed at once. The device supports par-
tial frame programming in which a frame may be partially programmed up to 10 separate program operations. The program size in
each of the 10 partial program operations is freely determined by the user and do not have to be equal to each other or to any preset
size. However, the user should ensure that the partial program units within a frame do not overlap as "0" data cannot be changed to
"1" data without an erase operation. To perform a partial frame program operation, the user only writes the partial frame data that is
to programmed. Just as in the standard frame program operation, an 80H command is followed by start address data. However, only
the partial program data need be divided when programming a frame in 10 partial program operations.
KM29W040AT, KM29W040AIT
R/B
I/O
FA
0
~
7
A2
43
CB
80H
81
28
Address & Data Input
A
0
32 Byte Data
E0
~A
7
& A
2A
8
~A
6
18
) of the Status Register. Only the Read Status command and Reset command are
D5
- - - - - - 32
10H
18
B5
7D
t
PROG
6F
AA
10th partial program start address (1Fh)
2nd partial program start address (04h)
9th partial program start address (18h)
1st partial program start address (00h)
E1
3rd partial program start address (06h)
FLASH MEMORY
D7
10th partial frame program data
:
2nd partial frame program data
:
3rd partial frame program data
9th partial frame program data
1st partial frame program data
0
) may be checked. The inter-
C0
:
:
Single
Frame
:
:
:
:
:
:
:
: