LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 472

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
Verilog
Here is the same design in Verilog.
The Soft SPI Interface is only needed to connect JTAG to the SPI Serial Flash interface. If the SPI Serial Flash will
be used by the user design, for instance as scratch memory, and background access via JTAG will not be required,
then the Soft SPI Interface is not needed, and the user code can access the SPI pins directly. Remember that the
configuration memory must start at address zero; any user defined memory space must be located above the con-
figuration data. It is recommended that an address above the maximum possible configuration size be chosen. For
instance if an ECP/EC20 device is being used, select a scratch pad starting address above 5.3Mb (see Table 21-3
in this document).
Locking the Pins
The last thing the user needs to do is tell ispLEVER which pins are connected to the SPI Serial Flash device (see
Figure 21-2 and Table 21-5). From the ispLEVER Project Navigator window click on the package name in the left
window, then double click on the Pre-Map Preference Editor in the right window (see Figure 21-15).
// Instantiate Soft SPI Interface
SPITOP spi_ip
endmodule
module SPITOP (SPI_PIN_C, SPI_PIN_D, SPI_PIN_SN, SPI_PIN_Q);
output
input
endmodule
module design_top(rst, sclk, cnt_out, spi_c, spi_d, spi_sn, spi_q) ;
input
output [7:0] cnt_out;
// SPI Serial Flash pins
input
output
reg [7:0]
// User code
always @ (posedge sclk or posedge rst)
begin
end
else
if (rst)
(
SPI_PIN_D, SPI_PIN_SN, SPI_PIN_C ;
SPI_PIN_Q;
.SPI_PIN_C(spi_c),
.SPI_PIN_D(spi_d),
.SPI_PIN_SN(spi_sn),
.SPI_PIN_Q(spi_q)
);
sclk, rst;
spi_q;
spi_d, spi_sn, spi_c;
cnt_out;
cnt_out = 2'h00;
cnt_out = cnt_out + 1;
21-16
SPI Serial Flash Programming Using ispJTAG
on LatticeECP/EC FPGAs