LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 380

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

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Lattice Semiconductor
LatticeECP-DSP sysDSP Usage Guide
MULT9X9ADDSUBSUM Primitive
MULT9X9ADDSUBSUM(CE0,CE1,CE2,CE3,CLK0,CLK1,CLK2,CLK3,RST0,RST1,RST2,RST3,SIGNEDAB,ADDNSUB1,AD
DNSUB3,
A00,A01,A02,A03,A04,A05,A06,A07,A08,
A10,A11,A12,A13,A14,A15,A16,A17,A18,
A20,A21,A22,A23,A24,A25,A26,A27,A28,
A30,A31,A32,A33,A34,A35,A36,A37,A38,
B00,B01,B02,B03,B04,B05,B06,B07,B08,
B10,B11,B12,B13,B14,B15,B16,B17,B18,
B20,B21,B22,B23,B24,B25,B26,B27,B28,
B30,B31,B32,B33,B34,B35,B36,B37,B38,
SRIA0,SRIA1,SRIA2,SRIA3,SRIA4,SRIA5,SRIA6,SRIA7,SRIA8,
SRIB0,SRIB1,SRIB2,SRIB3,SRIB4,SRIB5,SRIB6,SRIB7,SRIB8,
SROA0,SROA1,SROA2,SROA3,SROA4,SROA5,SROA6,SROA7,SROA8,
SROB0,SROB1,SROB2,SROB3,SROB4,SROB5,SROB6,SROB7,SROB8,
SUM0,SUM1,SUM2,SUM3,SUM4,SUM5,SUM6,SUM7,SUM8,
SUM9,SUM10,SUM11,SUM12,SUM13,SUM14,SUM15,SUM16,SUM17,
SUM18,SUM19) is black-box
{
property REG_INPUTA0_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_INPUTA0_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_INPUTA0_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_INPUTA1_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_INPUTA1_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_INPUTA1_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_INPUTA2_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_INPUTA2_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_INPUTA2_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_INPUTA3_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_INPUTA3_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_INPUTA3_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_INPUTB0_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_INPUTB0_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_INPUTB0_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_INPUTB1_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_INPUTB1_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_INPUTB1_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_INPUTB2_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_INPUTB2_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_INPUTB2_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_INPUTB3_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_INPUTB3_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_INPUTB3_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_PIPELINE0_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_PIPELINE0_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_PIPELINE0_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_PIPELINE1_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_PIPELINE1_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_PIPELINE1_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_PIPELINE2_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_PIPELINE2_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_PIPELINE2_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_PIPELINE3_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_PIPELINE3_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_PIPELINE3_RST {“RST0”,”RST1”,”RST2”,”RST3”};
property REG_OUTPUT_CLK {“NONE”,”CLK0”,”CLK1”,”CLK2”,”CLK3”};
property REG_OUTPUT_CE {“CE0”,”CE1”,”CE2”,”CE3”};
property REG_OUTPUT_RST {“RST0”,”RST1”,”RST2”,”RST3”};
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