LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 308
LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
PCB Layout Recommendations for VCCPLL and GNDPLL if Separate Pins are Available
It is best to connect VCCPLL to VCC at a single point using a filter and to create a separate GNDPLL plane directly
under it (tied via a single point to GND).
Separate islands for both VCCPLL and GNDPLL are recommended if applicable.
DCS Usage with Verilog
module dcs(clk0,clk1,sel,dcsout);
input clk0, clk1, sel;
output dcsout;
DCS DCSInst0 (.SEL(sel),.CLK0(clk0),.CLK1(clk1),.DCSOUT(dcsout));
defparam DCSInst0.DCSMODE = "CLK0";
endmodule
DCS Usage with VHDL
COMPONENT DCS
-- synthesis translate_off
-- synthesis translate_on
END COMPONENT;
begin
DCSInst0: DCS
-- synthesis translate_off
-- synthesis translate_on
);
attribute DCSMODE : string;
attribute DCSMODE of DCSinst0 : label is "POS";
GENERIC
PORT
GENERIC MAP(
PORT MAP
(
DCSMODE : string :=
);
(
CLK0
CLK1
SEL
DCSOUT
);
DCSMODE
)
(
SEL
CLK0
CLK1
DCSOUT
=> "POS"
:IN
:IN
:IN
:OUT
=>
=>
=>
=>
clksel,
dcsclk0,
sysclk1,
dcsclk
std_logic;
std_logic;
std_logic;
std_logic
"POS"
11-18
sysCLOCK PLL Design and Usage Guide
LatticeECP/EC and LatticeXP
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