LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 2
LFEC3E-3QN208I
Manufacturer Part Number
LFEC3E-3QN208I
Description
IC FPGA 3KLUTS 208PQFP
Manufacturer
Lattice
Series
EC3r
Datasheets
1.LFEC3E-5TN144C.pdf
(163 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFEC3E-3QN208I.pdf
(478 pages)
Specifications of LFEC3E-3QN208I
Number Of Logic Elements/cells
3100
Number Of Labs/clbs
-
Total Ram Bits
56320
Number Of I /o
145
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q6377645
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
September 2010
Section I. LatticeECP/EC Family Data Sheet
Introduction
Architecture
Features ............................................................................................................................................................. 1-1
Introduction ........................................................................................................................................................ 1-2
Architecture Overview ........................................................................................................................................ 2-1
PFU and PFF Blocks.......................................................................................................................................... 2-3
Routing............................................................................................................................................................... 2-7
Clock Distribution Network ................................................................................................................................. 2-7
Dynamic Clock Select (DCS) ........................................................................................................................... 2-11
sysMEM Memory ............................................................................................................................................. 2-12
sysDSP Block................................................................................................................................................... 2-14
Programmable I/O Cells (PIC) ......................................................................................................................... 2-21
DDR Memory Support...................................................................................................................................... 2-26
sysIO Buffer ..................................................................................................................................................... 2-28
Configuration and Testing ................................................................................................................................ 2-31
Slice .......................................................................................................................................................... 2-3
Primary Clock Sources.............................................................................................................................. 2-7
Secondary Clock Sources......................................................................................................................... 2-8
Clock Routing............................................................................................................................................ 2-8
sysCLOCK Phase Locked Loops (PLLs) .................................................................................................. 2-9
sysMEM Memory Block........................................................................................................................... 2-12
Bus Size Matching .................................................................................................................................. 2-12
RAM Initialization and ROM Operation ................................................................................................... 2-12
Memory Cascading ................................................................................................................................. 2-13
Single, Dual and Pseudo-Dual Port Modes............................................................................................. 2-13
Memory Core Reset ................................................................................................................................ 2-13
EBR Asynchronous Reset....................................................................................................................... 2-14
sysDSP Block Approach Compare to General DSP ............................................................................... 2-15
sysDSP Block Capabilities ...................................................................................................................... 2-15
MULT sysDSP Element .......................................................................................................................... 2-16
MAC sysDSP Element ............................................................................................................................ 2-16
MULTADD sysDSP Element................................................................................................................... 2-17
MULTADDSUM sysDSP Element........................................................................................................... 2-18
Clock, Clock Enable and Reset Resources ............................................................................................ 2-18
Signed and Unsigned with Different Widths............................................................................................ 2-19
OVERFLOW Flag from MAC .................................................................................................................. 2-19
IPexpress™............................................................................................................................................. 2-20
Optimized DSP Functions ....................................................................................................................... 2-20
Resources Available in the LatticeECP Family ....................................................................................... 2-20
DSP Performance of the LatticeECP Family........................................................................................... 2-20
PIO .......................................................................................................................................................... 2-22
DLL Calibrated DQS Delay Block ........................................................................................................... 2-26
Polarity Control Logic .............................................................................................................................. 2-28
sysIO Buffer Banks ................................................................................................................................. 2-28
Typical I/O Behavior During Power-up.................................................................................................... 2-30
Supported Standards .............................................................................................................................. 2-30
Hot Socketing.......................................................................................................................................... 2-31
LatticeECP/EC Family Handbook
1
Table of Contents
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