LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet
LFEC3E-3QN208I
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LFEC3E-3QN208I Summary of contents
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... LatticeECP/EC Family Handbook HB1000 Version 03.4, September 2010 ...
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... Configuration and Testing ................................................................................................................................ 2-31 © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Timing Diagrams .............................................................................................................................................. 3-18 PFU Timing Diagrams............................................................................................................................. 3-18 EBR Memory Timing Diagrams............................................................................................................... 3-19 LatticeECP/EC Family Timing Adders sysCLOCK PLL Timing .................................................................................................................................... 3-23 LatticeECP/EC sysCONFIG Port Timing Specifications .................................................................................. 3-24 Master Clock ........................................................................................................................................... 3-25 JTAG Port Timing Specifications ..................................................................................................................... 3-29 Switching Test Conditions................................................................................................................................ 3-30 Pinout Information Signal Descriptions ............................................................................................................................................ 4-1 PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin ...
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... Conventional Packaging ........................................................................................................................... 5-2 Lead-Free Packaging................................................................................................................................ 5-8 Supplemental Information For Further Information ...................................................................................................................................... 6-1 LatticeECP/EC Family Data Sheet Revision History LatticeECP/EC Family Data Sheet Revision History.......................................................................................... 7-1 Section II. LatticeECP/EC Family Technical Notes LatticeECP/EC and LatticeXP sysIO Usage Guide Introduction ........................................................................................................................................................ 8-1 sysIO Buffer Overview ....................................................................................................................................... 8-1 Supported sysIO Standards ...
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... WRITEMODE.......................................................................................................................................... 9-54 GSR ........................................................................................................................................................ 9-54 LatticeECP/EC and LatticeXP DDR Usage Guide Introduction ...................................................................................................................................................... 10-1 DDR SDRAM Interfaces Overview................................................................................................................... 10-1 Implementing DDR Memory Interfaces with the LatticeECP/EC Devices........................................................ 10-2 DQS Grouping......................................................................................................................................... 10-2 DDR Software Primitives......................................................................................................................... 10-5 Memory Read Implementation ................................................................................................................ 10-9 Data Read Critical Path......................................................................................................................... 10-12 DQS Postamble ...
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... Appendix D. Generic (Non-Memory) High-Speed DDR Interface .................................................................. 10-28 VHDL Implementation ........................................................................................................................... 10-28 Verilog Example .................................................................................................................................... 10-30 Preference File...................................................................................................................................... 10-31 Appendix E. List of Compatible DDR SDRAM ............................................................................................... 10-32 Appendix F. DDR400 Interface using the LatticeEC Evaluation Board.......................................................... 10-35 LatticeECP/EC and LatticeXP sysCLOCK PLL Design and Usage Guide Introduction ...................................................................................................................................................... 11-1 Features ........................................................................................................................................................... 11-1 Functional Description...................................................................................................................................... 11-1 PLL Divider and Delay Blocks ...
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... MULTICYCLE ....................................................................................................................................... 11-20 PERIOD ................................................................................................................................................ 11-20 PROHIBIT ............................................................................................................................................. 11-20 CLOCK_TO_OUT ................................................................................................................................. 11-20 INPUT_SETUP ..................................................................................................................................... 11-21 PLL_PHASE_BACK.............................................................................................................................. 11-21 Power Estimation and Management for LatticeECP/EC and LatticeXP Devices Introduction ...................................................................................................................................................... 12-1 Power Supply Sequencing and Hot Socketing................................................................................................. 12-1 Power Calculator Hardware Assumptions........................................................................................................ 12-1 Power Calculator.............................................................................................................................................. 12-1 Power Calculator Equations.................................................................................................................... 12-2 Starting the Power Calculator ...
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... MULT18X18ADDSUBSUM Primitive .................................................................................................... 15-15 MULT9X9 Primitive ............................................................................................................................... 15-16 MULT9X9MAC Primitive ....................................................................................................................... 15-17 MULT9X9ADDSUB Primitive ................................................................................................................ 15-18 MULT9X9ADDSUBSUM Primitive ........................................................................................................ 15-19 HDL Synthesis Coding Guidelines for Lattice Semiconductor FPGAs Introduction ...................................................................................................................................................... 16-1 General Coding Styles for FPGA ..................................................................................................................... 16-1 Hierarchical Coding................................................................................................................................. 16-1 Design Partitioning .................................................................................................................................. 16-2 State Encoding Methodologies for State Machines ................................................................................ 16-3 Coding Styles for FSM ...
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... Lattice Semiconductor HDL Design with Lattice Semiconductor FPGA Devices ................................................................................. 16-8 Lattice Semiconductor FPGA Synthesis Library ..................................................................................... 16-8 Implementing Multiplexers .................................................................................................................... 16-10 Clock Dividers ....................................................................................................................................... 16-10 Register Control Signals ....................................................................................................................... 16-12 Use PIC Features.................................................................................................................................. 16-14 Implementation of Memories................................................................................................................. 16-16 Preventing Logic Replication and Limited Fanout................................................................................. 16-16 Use ispLEVER Project Navigator Results for Device Utilization and Performance .............................. 16-17 Technical Support Assistance ...
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... BGA Board Layout Recommendations ............................................................................................................ 20-3 BGA Package Types........................................................................................................................................ 20-3 Further Information........................................................................................................................................... 20-3 Technical Support Assistance.......................................................................................................................... 20-3 Revision History ............................................................................................................................................... 20-3 SPI Serial Flash Programming Using ispJTAG on LatticeECP/EC FPGAs Introduction ...................................................................................................................................................... 21-1 Related Documents.......................................................................................................................................... 21-1 Hardware and Software Requirements ............................................................................................................ 21-1 SPI/SPIX Differences ....................................................................................................................................... 21-1 SPI Serial Flash Sizing............................................................................................................................ 21-2 Hardware ...
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... Section I. LatticeECP/EC Family Data Sheet DS1000 Version 02.7, February 2008 ...
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... LatticeECP devices only. © 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... LatticeECP devices without dedicated function blocks to achieve lower cost solutions. The LatticeECP/EC FPGA fabric, which was designed from the outset with low cost in mind, contains all the critical FPGA elements: LUT-based logic, distributed and embedded memory, PLLs and support for mainstream I/Os. ...
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... The LatticeECP/EC devices use 1.2V as their core volt- age. © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Interface sysCONFIG Programming Port (includes dedicated and dual use pins) Programmable Functional Unit (PFU) Figure 2-2. Simplified Block Diagram, LatticeECP-DSP Device (Top Level) Programmable I/O Cell (PIC) includes sysIO Interface sysCONFIG Programming Port (includes dedicated and dual use pins) ...
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... Lattice Semiconductor PFU and PFF Blocks The core of the LatticeECP/EC devices consists of PFU and PFF blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term PFU to refer to both PFU and PFF blocks ...
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... LUT4 output register bypass signals Q0, Q1 Register Outputs OFX0 Output of a LUT5 MUX OFX1 Output of a LUT6, LUT7, LUT8 FCO For the right most PFU the fast carry chain output 2-4 Architecture LatticeECP/EC Family Data Sheet Slice OFX1 FF/ Latch To Routing OFX0 ...
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... Dual port memories involve the pairing of two Slices, one Slice functions as the read-write port. The other companion Slice supports the read-only port. For more information about using RAM in LatticeECP/EC devices, please see the list of technical documentation at the end of this data sheet. Table 2-3. Number of Slices Required For Implementing Distributed RAM ...
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... Table 2-4. PFU Modes of Operation Logic LUT 4x8 or MUX 2x1 x 8 LUT 5x4 or MUX 4x1 x 4 LUT MUX 8x1 x 2 LUT 7x1 or MUX 16x1 These modes are not available in PFF blocks LatticeECP/EC Family Data Sheet WAD0 WAD1 WAD2 DO0 WAD3 DO1 DI0 DI1 WCK WRE ...
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... LatticeECP/EC devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing. LatticeECP/EC devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There are four dedicated clock inputs, one on each side of the device. Figure 2-6 shows the 20 primary clock sources. ...
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... From Routing Clock Routing The clock routing structure in LatticeECP/EC devices consists of four Primary Clock lines and a Secondary Clock network per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-8 shows this clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in Figure 2-9 ...
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... The setup and hold times of the device can be improved by programming a delay in the feedback or input path of the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro- DCS 4 Secondary Clocks per Quadrant Routing GND 2-9 Architecture LatticeECP/EC Family Data Sheet 1 DCS Clock to each slice ...
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... Delay Controlled VCO Adjust Oscillator Divider (CLKFB) RST CLKOP CLKI LOCK CLKFB DDA MODE DDAIZR DDAILAG DDAIDEL[2:0] 2-10 Architecture LatticeECP/EC Family Data Sheet LOCK Post Scalar Phase/Duty CLKOS Divider Select (CLKOP) CLKOP Secondary Clock CLKOK Divider (CLKOK) CLKOP CLKOS CLKOK LOCK ...
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... Figure 2-14 shows timing waveforms of the default DCS operating mode. The DCS block can be programmed to other modes. For more information about the DCS, please see the list of technical documentation at the end of this data sheet. LatticeECP/EC Family Data Sheet Description CLK0 DCS ...
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... SEL DCSOUT sysMEM Memory The LatticeECP/EC devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists Kbit RAM, with dedicated input and output registers. sysMEM Memory Block The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in a variety of depths and widths as shown in Table 2-6 ...
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... Lattice Semiconductor Memory Cascading Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual and Pseudo-Dual Port Modes Figure 2-15 shows the four basic memory configurations and their input/output names. In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array ...
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... Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled. sysDSP Block The LatticeECP-DSP family provides a sysDSP block, making it ideally suited for low cost, high performance Digital Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response (FIR) filters ...
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... General purpose DSP sysDSP Block Capabilities The sysDSP block in the LatticeECP-DSP family supports four functional elements in three 9, 18 and 36 data path widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned) of its operands. The operands in the LatticeECP-DSP family sysDSP Blocks can be either signed or unsigned but not mixed within a function element ...
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... The overflow conditions are provided later in this document. Figure 2-20 shows the MAC sysDSP element Shift Register Multiplier Input Data m Register Input To Register Multiplier Shift Register A Out 2-16 Architecture LatticeECP/EC Family Data Sheet x18 x36 — 2 — 1 — m+n m+n (default) x Output Pipeline Register CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) ...
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... Pipeline Pipe To Add/Sub Register Register Reg Input Pipeline Pipe To Add/Sub Register Register Reg Shift Register A Out 2-17 Architecture LatticeECP/EC Family Data Sheet Accumulator m+n+16 bits (default) m+n+16 bits (default) CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) m+n (default) Add/Sub Output ...
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... Input Data m Register Pipeline m Register Input Pipeline To Add/Sub0, Add/Sub1 Register Register Input Pipeline To Add/Sub0 Register Register Input Pipeline To Add/Sub1 Register Register Shift Register A Out 2-18 Architecture LatticeECP/EC Family Data Sheet CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) Add/Sub0 m+n+1 SUM m+n+2 m+n+2 m+n+1 Add/Sub1 Output ...
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... Signed Operation 2-19 Architecture LatticeECP/EC Family Data Sheet Two’s Complement Signed 9-Bits Signed 18-bits 000000101 000000000000000101 111111010 111111111111111010 3 2 Carry signal is generated for 1 one cycle when this 0 boundary is crossed ...
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... Lattice FPGAs. Optimized DSP Functions Lattice provides a library of optimized DSP IP functions. Some of the IPs planned for LatticeECP DSP are: Bit Cor- relators, Fast Fourier Transform, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/ Decoder, Turbo Encoder/Decoders and Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available DSP IPs ...
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... Register Block (2 Flip Flops DDRCLK IOLD0 Output Register Block (2 Flip Flops) INCK INDD INFF IPOS0 DI IPOS1 Input Muxes Register Block (5 Flip Flops) CLKO CEO LSR GSR CLKI CEI PIO B 2-21 Architecture LatticeECP/EC Family Data Sheet PADA "T" sysIO Buffer PADB "C" ...
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... PIO B PIO A PIO B PIO A PIO B PIO A PIO B PIO A PIO B PIO A PIO B 2-22 Architecture LatticeECP/EC Family Data Sheet Description PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" PADA "T" LVDS Pair PADB "C" ...
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... DDR Memory section of this data sheet. Figure 2-26. Input Register Diagram DI (From sysIO Buffer) Delay Block Fixed Delay DQS Delayed (From DQS Bus) CLK0 (From Routing) DDRCLKPOL (From DDR Polarity Control Bus) LatticeECP/EC Family Data Sheet SDR & Sync DDR Registers Registers D-Type D-Type /LATCH ...
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... A multiplexer running off the same clock selects the correct register for feeding to the output (D0). Figure 2-30 shows the design tool DDR primitives. The SDR output register has reset and clock enable available. The additional register for DDR operation does not have reset or clock enable available. LatticeECP/EC Family Data Sheet A B ...
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... In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0 D-Type /LATCH Q D Latch LE* *Latch is transparent when input is low ODDRXB CLK LSR 2-25 Architecture LatticeECP/EC Family Data Sheet OUTDDN sysIO 1 Buffer Programmed Control Q ...
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... Implementing high performance DDR memory interfaces requires dedicated DDR register structures in the input (for read operations) and in the output (for write operations). As indicated in the PIO Logic section, the LatticeEC devices provide this capability. In addition to these registers, the LatticeEC devices contain two elements to simplify the design of input structures for read operations: the DQS delay block and polarity control logic ...
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... Figure 2-32. DQS Local Bus. Delay Control Bus Polarity Control Bus DQS Bus DQS DQS Figure 2-33. DLL Calibration Bus and DQS/DQS Transition Distribution Delay Control Bus LatticeECP/EC Family Data Sheet PIO Input Register Block ( 5 Flip Flops) To Sync. Reg. GSR CLKI CEI To DDR DQS Reg. ...
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... Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the refer- enced input buffers. In the LatticeECP/EC devices, some dedicated I/O pins in a bank can be configured reference voltage supply pin. Each I/O is individually configurable based on the bank’s supply and reference volt- ages ...
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... V REF2(6) GND LatticeECP/EC devices contain two types of sysI/O buffer pairs. 1. Top and Bottom sysI/O Buffer Pairs (Single-Ended Outputs Only) The sysI/O buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also be configured as a differential input. ...
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... CCIO I/O banks that are critical to the application. For more information about controlling the output logic state with valid input logic levels during power-up in LatticeECP/EC devices, see the list of technical documentation at the end of this data sheet. The V ...
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... The following section describes the configuration and testing features of the LatticeECP/EC devices. IEEE 1149.1-Compliant Boundary Scan Testability All LatticeECP/EC devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes ...
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... All LatticeECP/EC devices support an internal logic analyzer diagnostic feature. The diagnostic features provide capabilities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace memory. This feature is enabled by Lattice’s ispTRACY. The ispTRACY utility is added into the user design at com- pile time. ...
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... Lattice Semiconductor Oscillator Every LatticeECP/EC device has an internal CMOS oscillator which is used to derive a master clock for configura- tion. The oscillator and the master clock run continuously. The default value of the master clock is 2.5MHz. Table 2- 15 lists all the available Master Clock frequencies. When a different Master Clock is selected during the design pro- cess, the following sequence takes place: 1 ...
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... LVCMOS and LVTTL only. © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, 2 CCIO V = 1.2V (MAX higher than transient current typically of 30ns in duration or less with a IH CCIO 3-2 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Min. Typ. Max. — — 10 — — 40 -30 — -150 30 — 150 30 — — ...
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... Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the V 3. Frequency 0MHz. 4. Pattern represents a “blank” configuration data file =25 C, power supplies at nominal voltage Per bank Over Recommended Operating Conditions Device LFEC1 LFEC3 LFECP6/LFEC6 LFECP10/LFEC10 LFECP15/LFEC15 LFECP20/LFEC20 LFECP33/LFEC33 6 3-3 DC and Switching Characteristics LatticeECP/EC Family Data Sheet 5 Typ GND. CCIO Units ...
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... Per bank Over Recommended Operating Conditions Devices LFEC1 LFEC3 LFECP6/LFEC6 LFECP10/LFEC10 LFECP15/LFEC15 LFECP20/LFEC20 LFECP33/LFEC33 LFEC1 LFEC3 LFECP6/LFEC6 LFECP10/LFEC10 LFECP15/LFEC15 LFECP20/LFEC20 LFECP33/LFEC33 LFEC1 LFEC3 LFECP6/LFEC6 7 LFECP10/LFEC10 LFECP15/LFEC15 LFECP20/LFEC20 LFECP33/LFEC33 3-4 DC and Switching Characteristics LatticeECP/EC Family Data Sheet 6 Typ 150 220 GND. CCIO ...
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... HSTL 18 Class III 1.71 LVDS 2.375 1 LVPECL 3.135 1 BLVDS 2.375 1 RSDS 2.375 1. Outputs are implemented with the addition of external resistors and Switching Characteristics LatticeECP/EC Family Data Sheet V CCIO Typ. Max. Min. 3.3 3.465 — 2.5 2.625 — 1.8 1.89 — 1.5 1.575 — ...
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... REF V + 0.1 3.6 0.4 REF V + 0.1 3.6 0.4 REF V + 0.1 3.6 0.4 REF V + 0.1 3.6 0.4 REF 3-6 DC and Switching Characteristics LatticeECP/EC Family Data Sheet 1 V Min (V) (mA) (mA) 20, 16, 12, -20, -16, -12 0.4 CCIO 0.2 0.1 CCIO 20, 16, 12, -20, -16, -12 ...
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... Ohm 100 Ohm 100 Ohm )/ 100 Ohm Driver outputs OD shorted 3-7 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Min. Typ. Max. 0 — 2.4 +/-100 — — 1.2 1.8 THD V /2 1.2 1.9 THD V /2 1.2 2.0 THD — — +/-10 — 1.38 1 ...
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... I and class II) are supported in this mode. LVDS25E The top and bottom side of LatticeECP/EC devices support LVDS outputs via emulated complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possible solution for point-to-point signals. ...
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... Lattice Semiconductor BLVDS The LatticeECP/EC devices support BLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals ...
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... Lattice Semiconductor LVPECL The LatticeECP/EC devices support differential LVPECL standard. This standard is emulated using complemen- tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point-to-point signals ...
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... Lattice Semiconductor RSDS The LatticeECP/EC devices support differential RSDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup- ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation ...
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... These timing numbers were generated using the ispLEVER design tool. Exact performance may vary with design and tool version. The tool uses internal parameters that have been characterized but are not tested on every device. 2. Applies to LatticeECP devices only. Timing v.G 0.30 ...
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... The user must determine this temperature and then use it to determine the derating factor based on the following derating tables: T °C. J Table 3-5. Delay Derating Table for Internal Blocks T °C J Commercial — — and Switching Characteristics LatticeECP/EC Family Data Sheet + (Power * JMAX AMAX JA Power Supply Voltage T °C J Industrial 1.14V 1.2V -40 ...
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... LFEC10 -0.93 LFEC15 -0.73 LFEC20 -0.51 LFEC33 -0.22 All — All — 0.19 All 0.67 3-14 DC and Switching Characteristics LatticeECP/EC Family Data Sheet -4 -3 Min. Max. Min. Max. — 6.11 — 7.13 — 6.85 — 7.99 — 6.72 — 7.84 — ...
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... Lattice Semiconductor LatticeECP/EC External Switching Characteristics (Continued) Parameter Description t Data Valid Before DQS DQVBS t Data Valid After DQS DQVAS f DDR Clock Frequency MAX_DDR 6 Primary and Secondary Clock 2 f Frequency for Primary Clock Tree MAX_PRI Clock Pulse Width for Primary t W_PRI Clock ...
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... DC and Switching Characteristics LatticeECP/EC Family Data Sheet - Max. Min. Max. Min. Max. 0.25 — 0.31 — 0.36 0.40 — 0.48 — 0.56 0.81 — ...
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... AdSub Input Register Hold Time HADSUB 1. Internal parameters are characterized but not tested on every device. 2. These parameters apply to LatticeECP devices only. 3. DSP Block is configured in Multiply Add/Sub Mode. 4. These parameters include the Adder Subtractor block in the path. Timing v.G 0.30 Over Recommended Operating Conditions Description Min ...
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... Timing Diagrams PFU Timing Diagrams Figure 3-6. Slice Single/Dual Port Write Cycle Timing Figure 3-7. Slice Single /Dual Port Read Cycle Timing WRE AD[3:0] DO[1:0] CK WRE AD AD[3:0] D DI[1:0] DO[1:0] Old Data Old Data 3-18 DC and Switching Characteristics LatticeECP/EC Family Data Sheet ...
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... Figure 3-9. Read/Write Mode with Input and Output Registers CLKA CSA WEA ADA t DIA DOA (Regs CO_EBR Mem(n) data from previous read output is only updated during a read cycle 3-19 DC and Switching Characteristics LatticeECP/EC Family Data Sheet CO_EBR CO_EBR COO_EBR COO_EBR D1 D0 ...
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... Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock ACCESS ACCESS ACCESS old A0 Data old A1 Data Three consecutive writes ACCESS ACCESS ACCESS D0 D1 3-20 DC and Switching Characteristics LatticeECP/EC Family Data Sheet ACCESS ACCESS ACCESS ...
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... HSTL18D_I Differential HSTL 18 class I HSTL18D_II Differential HSTL 18 class II HSTL18D_III Differential HSTL 18 class III HSTL15_I HSTL_15 class Over Recommended Operating Conditions Description -0.10 3-21 DC and Switching Characteristics LatticeECP/EC Family Data Sheet - 0.41 0.50 0.58 0.41 0.50 0.58 0.50 0.60 0.70 0.41 0.49 ...
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... LVCMOS timing measured with the load specified in Switching Test Conditions table of this document. 3. All other standards according to the appropriate specification. Timing v.G 0. (Continued) Over Recommended Operating Conditions Description 3-22 DC and Switching Characteristics LatticeECP/EC Family Data Sheet - 0.10 0.12 0.14 0.10 0.12 ...
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... Conditions Default Duty Cycle 3 Elected f >= 100MHz OUT f < 100MHz OUT Divider ratio = integer 3 At 90% or 10% 90% to 90% 10% to 10% 3-23 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Min. Typ. Max. 25 — 420 25 — 420 0.195 — 210 420 — 840 25 — ...
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... Lattice Semiconductor LatticeECP/EC sysCONFIG Port Timing Specifications Parameter sysCONFIG Byte Data Flow t Byte D[0:7] Setup Time to CCLK SUCBDI t Byte D[0:7] Hold Time to CCLK HCBDI t Clock to Dout in Flowthrough Mode CODO t CS[0:1] Setup Time to CCLK SUCS t CS[0:1] Hold Time to CCLK HCS t Write Signal Setup Time to CCLK ...
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... Lattice Semiconductor LatticeECP/EC sysCONFIG Port Timing Specifications (Continued) Parameter t CSSPIN Active Setup Time SOE t CSSPIN Low to First Clock Edge Setup Time CSPID f Max Frequency for SPI MAXSPI t SOSPI Data Setup Time Before CCLK SUSPI t SOSPI Data Hold Time After CCLK HSPI Timing v ...
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... In Master Parallel Mode the FPGA provides CCLK. In Slave Parallel Mode the external device provides CCLK. t BSCL t SUCS t SUWD t CORD Byte 0 Byte 1 t BSCL t SUCS t SUWD t t HCBDI SUCBDI Byte 0 Byte 1 Byte 2 3-26 DC and Switching Characteristics LatticeECP/EC Family Data Sheet t BSCYC t BSCH t HCS t HWD t DCB Byte 2 Byte n t BSCYC t BSCH t HCS t HWD t DCB Byte n ...
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... Time taken from Device Master Mode. 3. The CFG pins are normally static (hard wired). t SUMCDI t SSCL t SUSCDI t ICFG t VMC t SUCFG Valid whichever is the last to reach its V CCAUX MIN 3-27 DC and Switching Characteristics LatticeECP/EC Family Data Sheet t HMCDI t CODO t SSCH t HSCDI t CODO t HCFG . ...
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... DINIT INITN t CSSPI t CSSPIN CFGX CCLK SISPI/BUSY D7/SPID0 t PRGMRJ t DINIT t IODISS Wake-Up t MWC t IOENSS Capture OPCODE t CSPID CSCCLK t t SOCDO SOE 3-28 DC and Switching Characteristics LatticeECP/EC Family Data Sheet t t HCFG SUCFG Valid Clock 127 Clock 128 7 0 Valid Bitstream XXX ...
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... Over Recommended Operating Conditions Parameter t t BTS BTH t BTCPL t t BTCOEN BTCRH t BTCRS Data Captured t BTUPOEN 3-29 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Min Max — — 20 — 20 — 8 — 10 — 50 — — 10 — 10 — — 25 — — 25 — 25 — ...
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... Note: Output test conditions for all other interfaces are determined by the respective standards DUT CL* *CL Includes Test Fixture and Probe Capacitance 0pF 188¾ 0pF 3-30 DC and Switching Characteristics LatticeECP/EC Family Data Sheet Test Point Timing Ref. LVCMOS 3.3 = 1.5V LVCMOS 2 CCIO LVCMOS 1 CCIO LVCMOS 1 CCIO LVCMOS 1 CCIO V ...
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... TMS TCK © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com ...
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... CS1N WRITEN D[7:0]/SPID[0:7] DOUT/CSON DI/CSSPIN LatticeECP/EC Family Data Sheet I/O Test Data in pin. Used to load data into device using 1149.1 state machine. After power-up, this TAP port can be activated for configuration by sending I appropriate command. (Note: once a configuration port is selected it is locked ...
Page 79
... The DDR interface is designed for memories that support one DQS strobe per eight bits of data. In some packages, all the potential DDR data (DQ) pins may not be available. 3. PIC numbering definitions are provided in the “Signal Names” column of the Signal Descrip- tions table. LatticeECP/EC Family Data Sheet DDR Strobe (DQS) and PIO Within PIC Data (DQ) Pins ...
Page 80
... Pinout Information LatticeECP/EC Family Data Sheet LFECP6/EC6 LFECP/EC10 144- 208- 256- 484- 208- TQFP PQFP fpBGA fpBGA PQFP 97 147 195 224 147 112 72 ...
Page 81
... Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC33 672-fpBGA 484-fpBGA 672-fpBGA 400 360 200 180 509 373 ...
Page 82
... VCCAUX 37, 87 VCCPLL — GND, GND0-GND7 1, 14, 25, 35, 51, 68, 74 — LatticeECP/EC Family Data Sheet 144 TQFP 208 PQFP EC1, EC3: 26, 128, 135 EC1, EC3: 13, 92, 99 ECP/EC6: 11, 13, 92, 99 ECP/EC6: 24, 26, 128, 135 ECP/EC10: 5, 24, 26, 128, 135, 152 EC1: 187, 208 ...
Page 83
... AA21, Y23, Y22, AA24, Y24, J21, J22, J23, H22, G26, F26, E26, E25, F24, F23, E24, D24, E22, F22, E21, D22, G20, F20, D21, C21, C23, C22, B23, C24, D20, E19, B25, B24, B26, A25, C20, C19 ECP/EC33: None 4-7 Pinout Information LatticeECP/EC Family Data Sheet 672 fpBGA ...
Page 84
... PB10A C PB10B T PB11A C PB11B BDQS6 PB14A T VREF2_5 PB16A C VREF1_5 PB16B T PCLKT5_0 PB17A GND5 C PCLKC5_0 PB17B VCCAUX VCCIO4 T WRITEN PB18A C CS1N PB18B 4-8 Pinout Information LatticeECP/EC Family Data Sheet LFEC3 Pin Bank LVDS Dual Function - VREF2_7 7 C VREF1_7 PCLKT7_0 7 C PCLKC7_0 6 - TCK 6 ...
Page 85
... C PCLKC2_0 PR9B T PCLKT2_0 PR9A VREF1_2 PR2B VCCIO2 GND2 C PT25B T PT25A C PT22B T TDQS14 PT22A PT21A C PT20B T PT20A 4-9 Pinout Information LatticeECP/EC Family Data Sheet LFEC3 Pin Bank LVDS Dual Function 4 T VREF1_4 D0/SPID7 4 T D2/SPID5 4 C D1/SPID6 4 T BDQS22 4 C D3/SPID4 4 D4/SPID3 ...
Page 86
... C PCLKC0_0 PT17B GND0 T PCLKT0_0 PT17A C VREF1_0 PT16B T VREF2_0 PT16A PT15B C PT14B T TDQS6 PT14A C PT12B T PT12A C PT10B T PT10A VCCIO0 4-10 Pinout Information LatticeECP/EC Family Data Sheet LFEC3 Pin Bank LVDS Dual Function 1 C VREF2_1 1 T VREF1_1 PCLKC0_0 PCLKT0_0 0 C VREF1_0 0 T VREF2_0 ...
Page 87
... C PB13B 5 VCCIO5 5 BDQS6 PB14A 5 T PB14B 5 C PB15A 5 T PB15B 5 C PB16A 5 T 4-11 Pinout Information LatticeECP/EC Family Data Sheet LFECP6/EC6 Dual Function Pin Function Bank LVDS VCCIO7 7 VREF2_7 PL2A 7 T VREF1_7 PL2B 7 C PL7A 7 T PL7B 7 C PL8A 7 T PL8B ...
Page 88
... C PR11A 3 T CFG2 3 CFG1 3 CFG0 3 VCC - PROGRAMN 3 CCLK 3 INITN 3 GND - DONE 3 GND - 4-12 Pinout Information LatticeECP/EC Family Data Sheet LFECP6/EC6 Dual Function Pin Function Bank LVDS VREF1_5 PB16B 5 C PCLKT5_0 PB17A 5 T GND5 5 PCLKC5_0 PB17B 5 C VCCAUX - VCCIO4 4 WRITEN PB18A 4 T CS1N ...
Page 89
... PT4A 0 T 141 PT2B 0 C 142 PT2A 0 T 143 VCCIO0 0 GND0 144* - GND7 *Double bonded to the pin. LatticeECP/EC Family Data Sheet LFEC3 Pin Function Bank LVDS Dual Function VCC - PR9B 2 C PCLKC2_0 PR9A 2 T PCLKT2_0 PR8B 2 C PR8A 2 T PR7B ...
Page 90
... C PCLKC7_0 - LLM0_PLLT_IN_A 6 C LLM0_PLLC_IN_A 6 T LLM0_PLLT_FB_A 6 C LLM0_PLLC_FB_A 4-14 Pinout Information LatticeECP/EC Family Data Sheet LFEC3 Pin Function Bank LVDS Dual Function GND0 - GND7 VCCIO7 7 PL2A 7 T PL2B PL3B 7 PL4A 7 T PL4B 7 C PL5A 7 T PL5B 7 C PL6A 7 T VCCIO7 ...
Page 91
... BDQS6 VREF2_5 5 C VREF1_5 5 T PCLKT5_0 PCLKC5_0 - 4-15 Pinout Information LatticeECP/EC Family Data Sheet LFEC3 Bank LVDS Dual Function PL15A 6 T LDQS15 PL15B 6 C PL16A 6 T PL16B 6 C PL17A 6 T PL17B 6 C PL18A 6 T VREF1_6 PL18B 6 C VREF2_6 VCCIO6 6 GND5 - GND6 ...
Page 92
... T RLM0_PLLT_FB_A 3 C RLM0_PLLC_IN_A 3 T RLM0_PLLT_IN_A DI/CSSPIN 3 T DOUT/CSON 3 C BUSY/SISPI 3 T D7/SPID0 3 3 4-16 Pinout Information LatticeECP/EC Family Data Sheet LFEC3 Bank LVDS Dual Function VCCIO4 4 PB18A 4 T WRITEN PB18B 4 C PB19A 4 T VREF1_4 PB19B 4 C PB20A 4 T VREF2_4 PB20B ...
Page 93
... C VREF1_2 2 T VREF2_2 TDQS14 4-17 Pinout Information LatticeECP/EC Family Data Sheet LFEC3 Pin Function Bank LVDS Dual Function CFG0 3 VCC - PROGRAMN 3 CCLK 3 INITN 3 GND - DONE 3 GND - VCC - VCCAUX - PR9B 2 C GND2 2 PR9A 2 T PR8B 2 C PR8A 2 T ...
Page 94
... T VREF2_0 TDQS6 4-18 Pinout Information LatticeECP/EC Family Data Sheet LFEC3 Bank LVDS Dual Function PT21A 1 T PT20B 1 C PT20A 1 T PT19B 1 C VREF2_1 PT19A 1 T VREF1_1 PT18B 1 C PT18A 1 T VCCIO1 1 VCCAUX - PT17B 0 C PCLKC0_0 GND0 0 PT17A 0 T PCLKT0_0 PT16B 0 ...
Page 95
... PCLKC7_0 - LLM0_PLLT_IN_A 6 C LLM0_PLLC_IN_A 6 T LLM0_PLLT_FB_A 6 C LLM0_PLLC_FB_A 4-19 Pinout Information LatticeECP/EC Family Data Sheet LFECP10/LFEC10 Bank LVDS Dual Function GND0 - GND7 VCCIO7 7 PL2A 7 T VREF2_7 PL2B 7 C VREF1_7 VCC - GND - PL12B 7 PL13A 7 T PL13B 7 C PL14A 7 T PL14B 7 C PL15A ...
Page 96
... BDQS14 VREF2_5 5 C VREF1_5 5 T PCLKT5_0 PCLKC5_0 - 4-20 Pinout Information LatticeECP/EC Family Data Sheet LFECP10/LFEC10 Bank LVDS Dual Function PL33A 6 T LDQS33 PL33B 6 C PL34A 6 T PL34B 6 C PL35A 6 T PL35B 6 C PL36A 6 T VREF1_6 PL36B 6 C VREF2_6 VCCIO6 6 GND5 - GND6 ...
Page 97
... T RLM0_PLLT_FB_A 3 C RLM0_PLLC_IN_A 3 T RLM0_PLLT_IN_A DI/CSSPIN 3 T DOUT/CSON 3 C BUSY/SISPI 3 T D7/SPID0 3 3 4-21 Pinout Information LatticeECP/EC Family Data Sheet LFECP10/LFEC10 Pin Function Bank LVDS Dual Function VCCIO4 4 PB26A 4 T PB26B 4 C PB27A 4 T PB27B 4 C PB28A 4 T PB28B 4 C PB29A ...
Page 98
... RDQS6 VREF1_2 2 T VREF2_2 TDQS22 4-22 Pinout Information LatticeECP/EC Family Data Sheet LFECP10/LFEC10 Pin Function Bank LVDS Dual Function CFG0 3 VCC - PROGRAMN 3 CCLK 3 INITN 3 GND - DONE 3 GND - VCC - VCCAUX - PR18B 2 C GND2 2 PR18A 2 T PR17B 2 C PR17A 2 T PR16B 2 C PR16A ...
Page 99
... T TDQS14 TDQS6 4-23 Pinout Information LatticeECP/EC Family Data Sheet LFECP10/LFEC10 Bank LVDS Dual Function PT29A 1 T PT28B 1 C PT28A 1 T PT27B 1 C VREF2_1 PT27A 1 T VREF1_1 PT26B 1 C PT26A 1 T VCCIO1 1 VCCAUX - PT25B 0 C PCLKC0_0 GND0 0 PT25A 0 T PCLKT0_0 PT24B 0 C VREF1_0 ...
Page 100
... L4 VCCJ 6 LFEC3 LVDS Dual Function Ball Function T VREF2_7 C VREF1_7 LDQS6 PCLKT7_0 C PCLKC7_0 4-24 Pinout Information LatticeECP/EC Family Data Sheet LFECP6/LFEC6 Bank LVDS Dual Function GND7 7 PL2A 7 T PL2B 7 C PL3A 7 T PL3B 7 C PL4A 7 T PL4B 7 C PL5A 7 T PL5B 7 C ...
Page 101
... C T LDQS15 VREF1_6 C VREF2_6 BDQS6 4-25 Pinout Information LatticeECP/EC Family Data Sheet LFECP6/LFEC6 Bank LVDS Dual Function PL20A 6 T LLM0_PLLT_IN_A PL20B 6 C LLM0_PLLC_IN_A PL21A 6 T LLM0_PLLT_FB_A PL21B 6 C LLM0_PLLC_FB_A PL22A 6 T PL22B 6 C PL23A 6 T GND6 6 PL23B 6 C PL24A 6 T PL24B ...
Page 102
... D1/SPID6 T BDQS22 C D3/SPID4 T C D4/SPID3 T C D5/SPID2 T C D6/SPID1 C VREF2_3 T VREF1_3 RDQS15 C RLM0_PLLC_FB_A 4-26 Pinout Information LatticeECP/EC Family Data Sheet LFECP6/LFEC6 Bank LVDS Dual Function GND5 5 PB13B 5 C PB14A 5 T PB14B 5 C PB15A 5 T PB15B 5 C PB16A 5 T VREF2_5 PB16B 5 C VREF1_5 ...
Page 103
... C RLM0_PLLC_IN_A T RLM0_PLLT_IN_A C DI/CSSPIN T DOUT/CSON C BUSY/SISPI T D7/SPID0 PROGRAMN C PCLKC2_0 T PCLKT2_0 RDQS6 C T 4-27 Pinout Information LatticeECP/EC Family Data Sheet LFECP6/LFEC6 Bank LVDS Dual Function PR23A 3 T RLM0_PLLT_FB_A PR22B 3 C RLM0_PLLC_IN_A PR22A 3 T RLM0_PLLT_IN_A PR21B 3 C DI/CSSPIN PR21A 3 T DOUT/CSON PR20B 3 C BUSY/SISPI ...
Page 104
... TDQS22 VREF2_1 T VREF1_1 PCLKC0_0 T PCLKT0_0 C VREF1_0 T VREF2_0 TDQS14 4-28 Pinout Information LatticeECP/EC Family Data Sheet LFECP6/LFEC6 Bank LVDS Dual Function PR4B 2 C PR4A 2 T PR3B 2 C PR3A 2 T PR2B 2 C VREF1_2 PR2A 2 T VREF2_2 GND2 2 GND1 1 GND1 1 PT26B 1 C PT26A 1 T PT25B ...
Page 105
... T16 GND - E12 VCC - LFEC3 LVDS Dual Function Ball Function TDQS6 4-29 Pinout Information LatticeECP/EC Family Data Sheet LFECP6/LFEC6 Bank LVDS Dual Function PT11B 0 C PT11A 0 T PT10B 0 C PT10A 0 T PT9B 0 C GND0 0 PT9A 0 T PT8B 0 C PT8A 0 T PT7B 0 ...
Page 106
... LVDS Dual Function Ball Function VCCAUX VCCAUX VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO7 VCCIO7 4-30 Pinout Information LatticeECP/EC Family Data Sheet LFECP6/LFEC6 Bank LVDS Dual Function VCC - VCC - VCC - VCC - VCC - - - ...
Page 107
... PCLKC7_0 PL22B XRES T PL24A C PL24B T PL25A C PL25B T PL26A C PL26B T PL27A GND6 C PL27B T LDQS24 PL28A C PL28B T PL29A C PL29B T PL30A C PL30B T PL31A GND6 C PL31B TCK TDI 4-31 Pinout Information LatticeECP/EC Family Data Sheet LFECP15/LFEC15 Bank LVDS Dual Function VREF2_7 7 C VREF1_7 LDQS19 PCLKT7_0 ...
Page 108
... GND5 T PB10A C PB10B T PB11A C PB11B T PB12A C PB12B T PB13A GND5 C PB13B T BDQS14 PB14A C PB14B T PB15A C PB15B T PB16A C PB16B T PB17A GND5 C PB17B T PB18A 4-32 Pinout Information LatticeECP/EC Family Data Sheet LFECP15/LFEC15 Bank LVDS Dual Function LLM0_PLLT_IN_A 6 C LLM0_PLLC_IN_A 6 T LLM0_PLLT_FB_A 6 C LLM0_PLLC_FB_A LDQS41 ...
Page 109
... PB29B T BDQS30 PB30A C D3/SPID4 PB30B T PB31A C D4/SPID3 PB31B T PB32A C D5/SPID2 PB32B T PB33A GND4 C D6/SPID1 PB33B PB34A GND4 GND4 GND4 GND4 GND3 C VREF2_3 PR44B T VREF1_3 PR44A 4-33 Pinout Information LatticeECP/EC Family Data Sheet LFECP15/LFEC15 Bank LVDS Dual Function BDQS22 VREF2_5 5 C VREF1_5 5 T ...
Page 110
... PR30B T PR30A C PR29B T PR29A C PR28B T RDQS24 PR28A C PR27B GND3 T PR27A C PR26B T PR26A C PR25B T PR25A C PR24B T PR24A C PCLKC2_0 PR22B GND2 4-34 Pinout Information LatticeECP/EC Family Data Sheet LFECP15/LFEC15 Bank LVDS Dual Function RDQS41 3 C RLM0_PLLC_FB_A RLM0_PLLT_FB_A 3 C RLM0_PLLC_IN_A 3 T RLM0_PLLT_IN_A 3 C DI/CSSPIN 3 ...
Page 111
... PT34B T PT34A C PT33B GND1 T PT33A C PT32B T PT32A C PT31B T PT31A C PT30B T TDQS30 PT30A C PT29B GND1 T PT29A C PT28B T PT28A C VREF2_1 PT27B T VREF1_1 PT27A C PT26B T PT26A 4-35 Pinout Information LatticeECP/EC Family Data Sheet LFECP15/LFEC15 Bank LVDS Dual Function 2 T PCLKT2_0 RDQS19 VREF1_2 2 T VREF2_2 ...
Page 112
... PT15B T PT15A C PT14B T TDQS14 PT14A C PT13B GND0 T PT13A C PT12B T PT12A C PT11B T PT11A C PT10B T PT10A GND0 GND0 GND GND GND GND GND 4-36 Pinout Information LatticeECP/EC Family Data Sheet LFECP15/LFEC15 Bank LVDS Dual Function 0 C PCLKC0_0 PCLKT0_0 0 C VREF1_0 0 T VREF2_0 TDQS22 ...
Page 113
... VCCAUX VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCC VCC VCC VCC 4-37 Pinout Information LatticeECP/EC Family Data Sheet LFECP15/LFEC15 Bank LVDS Dual Function - - - - - - - - - - - - - - - - - - ...
Page 114
... PL9A 7 T PCLKT7_0 GND GND7 7 K1 PL9B 7 C PCLKC7_0 L3 XRES 6 L4 PL11A PL11B PL12A PL12B 6 C LatticeECP/EC Family Data Sheet LFECP10/LFEC10 Ball Ball Dual Number Function Bank LVDS Function GND GND7 7 D4 PL2A 7 T VREF2_7 E4 PL2B 7 C VREF1_7 C3 PL3A PL3B PL4A ...
Page 115
... PL24B 6 C AA1 PL25A 6 T AA2 PL25B PL26A PL26B PL27A 6 T VREF1_6 Y3 PL27B 6 C VREF2_6 GND GND6 6 LatticeECP/EC Family Data Sheet LFECP10/LFEC10 Ball Ball Dual Number Function Bank LVDS Function M4 PL22A PL22B PL23A 6 T GND GND6 6 M2 PL23B PL24A 6 T LDQS24 ...
Page 116
... GND5 5 AB9 PB13B 5 C AA10 PB14A 5 T BDQS14 AA9 PB14B 5 C Y11 PB15A 5 T AA11 PB15B 5 C V11 PB16A 5 T VREF2_5 LatticeECP/EC Family Data Sheet LFECP10/LFEC10 Ball Ball Dual Number Function Bank LVDS Function GND GND5 5 V7 PB2A PB2B PB3A PB3B 5 C ...
Page 117
... U15 NC - V16 NC - U16 NC - Y17 NC - V17 NC - AB20 NC - GND - - AA19 NC - Y16 NC - 4-41 Pinout Information LatticeECP/EC Family Data Sheet LFECP/LFEC15 Ball Ball Number Function Bank LVDS V12 PB24B 5 C AB10 PB25A 5 T GND GND5 5 AB11 PB25B 5 C Y12 PB26A 4 T U11 PB26B 4 C W12 ...
Page 118
... P19 NC - P18 NC - P21 PR27B 3 C GND GND3 3 P22 PR27A 3 T N21 PR26B 3 C 4-42 Pinout Information LatticeECP/EC Family Data Sheet LFECP/LFEC15 Ball Ball Number Function Bank LVDS W17 PB46B 4 C AA20 PB47A 4 T Y19 PB47B 4 C Y18 PB48A 4 T W18 PB48B ...
Page 119
... H18 NC - D21 NC - GND - - C22 NC - G19 NC - G18 NC - F20 NC - F19 NC - E20 NC - D20 NC - LatticeECP/EC Family Data Sheet LFECP10/LFEC10 Ball Ball Dual Number Function Bank LVDS Function N22 PR26A 3 T N19 PR25B 3 C N18 PR25A 3 T M21 PR24B 3 C L20 PR24A 3 T RDQS24 L21 PR23B ...
Page 120
... T A13 PT33B 1 C GND GND1 1 B13 PT33A 1 T E14 PT32B 1 C C13 PT32A 1 T 4-44 Pinout Information LatticeECP/EC Family Data Sheet LFECP/LFEC15 Ball Ball Number Function Bank LVDS C21 PR5B 2 C C20 PR5A 2 T F18 PR4B 2 C E18 PR4A 2 T B22 ...
Page 121
... C8 PT5A PT4B PT4A PT3B PT3A PT2B PT2A 0 T GND GND0 0 LatticeECP/EC Family Data Sheet LFECP10/LFEC10 Ball Ball Dual Number Function Bank LVDS Function F14 PT31B 1 C D14 PT31A 1 T E13 PT30B 1 C G13 PT30A 1 T TDQS30 A12 PT29B 1 C GND GND1 ...
Page 122
... GND - L14 GND - L9 GND - M10 GND - M11 GND - M12 GND - M13 GND - M14 GND - M9 GND - N10 GND - N11 GND - N12 GND - LatticeECP/EC Family Data Sheet LFECP10/LFEC10 Ball Ball Dual Number Function Bank LVDS Function A4 PT9B PT9A PT8B PT8A PT7B PT7A PT6B ...
Page 123
... VCCIO3 3 R12 VCCIO4 4 R13 VCCIO4 4 R14 VCCIO4 4 T12 VCCIO4 4 R10 VCCIO5 5 R11 VCCIO5 5 R9 VCCIO5 5 4-47 Pinout Information LatticeECP/EC Family Data Sheet LFECP/LFEC15 Ball Ball Number Function Bank LVDS N13 GND - N14 GND - N9 GND - P10 GND - P11 GND - P12 GND - P13 ...
Page 124
... T16 VCCAUX - T7 VCCAUX - T8 VCCAUX - J6 VCC - J17 VCC - P6 VCC - P17 VCC - AB2 NC - A21 NC - LatticeECP/EC Family Data Sheet LFECP10/LFEC10 Ball Ball Dual Number Function Bank LVDS Function T11 VCCIO5 5 M7 VCCIO6 6 M8 VCCIO6 6 N8 VCCIO6 6 P8 VCCIO6 6 J8 VCCIO7 7 K8 VCCIO7 7 L7 VCCIO7 ...
Page 125
... GND GND LDQS19 4-49 Pinout Information LatticeECP/EC Family Data Sheet LFECP/LFEC33 Dual Function GND7 7 PL2A 7 T VREF2_7 PL2B 7 C VREF1_7 GND7 7 PL10A 7 T PL10B 7 C PL11A 7 T PL11B 7 C PL12A 7 T PL12B 7 C GND7 7 PL14A 7 T LDQS14 PL14B 7 C PL15A 7 T PL15B ...
Page 126
... GND LDQS36 GND LLM0_PLLT_IN_A V1 C LLM0_PLLC_IN_A V2 4-50 Pinout Information LatticeECP/EC Family Data Sheet LFECP/LFEC33 Dual Function PL33B 7 C PL34A 7 T PCLKT7_0 GND7 7 PL34B 7 C PCLKC7_0 XRES 6 PL36A 6 T PL36B 6 C PL37A 6 T PL37B 6 C PL38A 6 T PL38B 6 C PL39A 6 T GND6 ...
Page 127
... AA3 GND C AB3 T BDQS14 AA5 AA4 GND C AB4 4-51 Pinout Information LatticeECP/EC Family Data Sheet LFECP/LFEC33 Dual Function PL54A 6 T LLM0_PLLT_FB_A PL54B 6 C LLM0_PLLC_FB_A PL55A 6 T PL55B 6 C PL56A 6 T GND6 6 PL56B 6 C PL57A 6 T LDQS57 PL57B 6 C PL58A 6 T PL58B ...
Page 128
... W13 C D0/SPID7 U13 T D2/SPID5 AA12 GND C D1/SPID6 AB12 T BDQS38 T13 C D3/SPID4 V13 T W14 C D4/SPID3 U14 T Y13 4-52 Pinout Information LatticeECP/EC Family Data Sheet LFECP/LFEC33 Dual Function PB21A 5 T GND5 5 PB21B 5 C PB22A 5 T BDQS22 PB22B 5 C PB23A 5 T PB23B 5 C PB24A 5 ...
Page 129
... BDQS54 Y16 C W17 T AA20 C Y19 T Y18 C W18 T T17 C U17 GND GND GND GND C VREF2_3 W20 4-53 Pinout Information LatticeECP/EC Family Data Sheet LFECP/LFEC33 Dual Function PB40B 4 C D5/SPID2 PB41A 4 T GND4 4 PB41B 4 C D6/SPID1 PB42A 4 T PB42B 4 C PB43A 4 T PB43B ...
Page 130
... R18 C U22 GND T T22 C R21 T R22 C P20 T N20 C P19 T P18 C P21 GND T P22 C N21 T N22 4-54 Pinout Information LatticeECP/EC Family Data Sheet LFECP/LFEC33 Dual Function PR68A 3 T VREF1_3 GND3 3 GND3 3 PR59B 3 C PR59A 3 T PR58B 3 C PR58A 3 T PR57B 3 C PR57A 3 T ...
Page 131
... C G21 T G20 GND C J18 T H19 C J19 T H20 C H17 T H18 C RUM0_PLLC_FB_A D21 GND GND T RUM0_PLLT_FB_A C22 4-55 Pinout Information LatticeECP/EC Family Data Sheet LFECP/LFEC33 Dual Function PR41B 3 C PR41A 3 T PR40B 3 C PR40A 3 T RDQS40 PR39B 3 C GND3 3 PR39A 3 T PR38B 3 C PR38A ...
Page 132
... C E17 T C17 C F16 T E16 C F15 T D16 C B18 GND T A19 C B17 T A18 C B16 T A17 4-56 Pinout Information LatticeECP/EC Family Data Sheet LFECP/LFEC33 Dual Function PR16B 2 C RUM0_PLLC_IN_A PR16A 2 T RUM0_PLLT_IN_A PR15B 2 C PR15A 2 T PR14B 2 C PR14A 2 T RDQS14 PR13B 2 C GND2 ...
Page 133
... A10 C VREF1_0 E12 T VREF2_0 E11 C B11 T C11 TDQS30 B10 C A9 GND D11 T C10 C A7 4-57 Pinout Information LatticeECP/EC Family Data Sheet LFECP/LFEC33 Dual Function PT46B 1 C PT46A 1 T TDQS46 PT45B 1 C GND1 1 PT45A 1 T PT44B 1 C PT44A 1 T PT43B 1 C PT43A 1 ...
Page 134
... TDQS14 GND GND GND A1 A22 AB1 4-58 Pinout Information LatticeECP/EC Family Data Sheet LFECP/LFEC33 Dual Function PT27A 0 T PT26B 0 C PT26A 0 T PT25B 0 C GND0 0 PT25A 0 T PT24B 0 C PT24A 0 T PT23B 0 C PT23A 0 T PT22B 0 C PT22A 0 T TDQS22 PT21B ...
Page 135
... GND - P14 GND - P9 GND - R15 GND - R8 GND - J16 VCC - J7 VCC - K16 VCC - LatticeECP/EC Family Data Sheet Dual Function Ball Number Ball Function Bank LVDS AB22 H15 H8 J10 J11 J12 J13 J14 J9 K10 K11 K12 K13 K14 K9 L10 L11 L12 L13 L14 ...
Page 136
... VCCIO5 5 M7 VCCIO6 6 M8 VCCIO6 6 N8 VCCIO6 6 P8 VCCIO6 6 J8 VCCIO7 7 K8 VCCIO7 7 L7 VCCIO7 7 LatticeECP/EC Family Data Sheet Dual Function Ball Number Ball Function Bank LVDS K17 K6 K7 L17 L6 M17 M6 N16 N17 N6 N7 P16 P7 G11 VCCIO0 H10 VCCIO0 H11 VCCIO0 H9 ...
Page 137
... J17 VCC - 1 P6 VCC - 1 P17 VCC - AB2 NC - A21 Tied to V CCPLL. LatticeECP/EC Family Data Sheet Dual Function Ball Number Ball Function Bank LVDS L8 VCCIO7 G15 VCCAUX G16 VCCAUX G7 VCCAUX G8 VCCAUX H16 VCCAUX H7 VCCAUX R16 VCCAUX R7 VCCAUX T15 VCCAUX T16 VCCAUX ...
Page 138
... LUM0_PLLC_IN_A G6 PL16B LUM0_PLLT_FB_A H4 PL17A GND GND7 LUM0_PLLC_FB_A G4 PL17B H6 PL19A J7 PL19B G5 PL20A H5 PL20B H3 PL21A J3 PL21B H2 PL22A GND GND7 J2 PL22B J4 PL23A J5 PL23B K4 PL24A K5 PL24B J6 PL25A 4-62 Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC33 Ball Dual Bank LVDS Function VREF2_7 7 C VREF1_7 7 T LDQS6 ...
Page 139
... T P3 PL28B PL29A PL29B PL30A PL30B PL31A 6 T GND GND6 6 R3 PL31B PL32A 6 T LatticeECP/EC Family Data Sheet Ball Ball Dual Function Number Function K6 PL25B F1 PL26A GND GND7 G1 PL26B H1 PL27A J1 PL27B K2 PL28A K1 PL28B K3 PL29A L3 PL29B L2 PL30A GND GND7 L1 PL30B LDQS19 M3 PL31A M4 ...
Page 140
... LLM0_PLLC_FB_A W6 PL54B Y1 PL55A Y2 PL55B W3 PL56A GND GND6 W4 PL56B LDQS45 AA1 PL57A AB1 PL57B Y4 PL58A Y3 PL58B AC1 PL59A AB2 PL59B AA2 PL60A GND GND6 AA3 PL60B W5 PL61A Y5 PL61B 4-64 Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC33 Ball Dual Bank LVDS Function LDQS48 ...
Page 141
... PB11A 5 T AB9 PB11B 5 C AF3 PB12A 5 T AD9 PB12B 5 C AE4 PB13A 5 T GND GND5 5 LatticeECP/EC Family Data Sheet Ball Ball Dual Function Number Function Y6 PL62A W7 PL62B AA4 PL63A AB3 PL63B AC2 PL64A GND GND6 AC3 PL64B AA5 PL65A AB5 ...
Page 142
... C AA12 PB30A 5 T AB12 PB30B 5 C AE13 PB31A 5 T AF13 PB31B 5 C AD13 PB32A 5 T LatticeECP/EC Family Data Sheet Ball Ball Dual Function Number Function AF4 PB13B BDQS14 AE5 PB14A AA9 PB14B AF5 PB15A Y10 PB15B AD6 PB16A AC10 PB16B AF6 ...
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... C AF21 PB49A 4 T GND GND4 4 AF20 PB49B 4 C AE21 PB50A 4 T AC17 PB50B 4 C LatticeECP/EC Family Data Sheet Ball Ball Dual Function Number Function VREF1_5 AC13 PB32B PCLKT5_0 AF14 PB33A GND GND5 PCLKC5_0 AE14 PB33B WRITEN AA13 PB34A CS1N AB13 ...
Page 144
... GND3 3 AC23 PR48B 3 C AC24 PR48A 3 T AD24 NC - AD25 NC - AE26 NC - AD26 NC - Y20 NC - LatticeECP/EC Family Data Sheet Ball Ball Dual Function Number Function AF22 PB51A AB17 PB51B AE22 PB52A AA18 PB52B AE19 PB53A GND GND4 AE20 PB53B BDQS54 AA19 PB54A Y18 PB54B ...
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... V21 CFG1 V23 CFG0 V22 PROGRAMN V20 CCLK V25 INITN U20 DONE V26 PR51B GND GND3 U26 PR51A U24 PR50B U25 PR50A U23 PR49B U22 PR49A 4-69 Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC33 Ball Dual Bank LVDS Function 3 T RDQS65 ...
Page 146
... C L21 PR19A 2 T L22 PR18B 2 C GND GND2 2 L23 PR18A 2 T L25 PR17B 2 C LatticeECP/EC Family Data Sheet Ball Ball Dual Function Number Function U21 PR48B RDQS36 T21 PR48A T25 PR47B GND GND3 T26 PR47A T22 PR46B T23 PR46A T24 ...
Page 147
... H21 T G21 C D26 T RDQS6 D25 C F21 GND T G22 C G24 T G23 C C26 T C25 F24 GND F23 4-71 Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC33 Ball Function Bank LVDS Function PR29A 2 T PR28B 2 C PR28A 2 T PR27B 2 C PR27A 2 T PR26B 2 C GND2 ...
Page 148
... A23 C E18 T D19 C F19 T B22 C G19 T TDQS54 B21 C D18 GND T C18 C F18 T A22 C G18 4-72 Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC33 Ball Function Bank LVDS Function PR8B 2 C PR8A 2 T PR7B 2 C PR7A 2 T PR6B 2 C PR6A 2 T RDQS6 PR2B ...
Page 149
... T F14 PT34B 1 C C14 PT34A 1 T B14 PT33B 0 C GND GND0 0 A14 PT33A 0 T LatticeECP/EC Family Data Sheet Ball Ball Dual Function Number Function A21 PT51A E17 PT50B B17 PT50A C17 PT49B GND GND1 D17 PT49A F17 PT48B E20 PT48A ...
Page 150
... B7 C E11 G11 G10 C10 GND T D10 C F10 E10 TDQS14 D9 4-74 Pinout Information LatticeECP/EC Family Data Sheet LFECP/EC33 Ball Function Bank LVDS Function PT32B 0 C VREF1_0 PT32A 0 T VREF2_0 PT31B 0 C PT31A 0 T PT30B 0 C PT30A 0 T TDQS30 PT29B 0 C GND0 0 ...
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... K16 GND - L10 GND - L11 GND - L12 GND - L13 GND - L14 GND - L15 GND - L16 GND - L17 GND - LatticeECP/EC Family Data Sheet Ball Ball Dual Function Number Function A5 PT13B GND GND0 A4 PT13A F9 PT12B B6 PT12A E9 PT11B C8 PT11A G8 PT10B B5 PT10A A3 PT9B GND GND0 ...
Page 152
... T13 GND - T14 GND - T15 GND - T16 GND - T17 GND - U10 GND - U11 GND - LatticeECP/EC Family Data Sheet Ball Ball Dual Function Number Function M10 GND M11 GND M12 GND M13 GND M14 GND M15 GND M16 GND M17 GND N10 ...
Page 153
... H13 VCCIO0 0 J10 VCCIO0 0 J11 VCCIO0 0 J12 VCCIO0 0 J13 VCCIO0 0 H14 VCCIO1 1 H15 VCCIO1 1 LatticeECP/EC Family Data Sheet Ball Ball Dual Function Number Function U12 GND U13 GND U14 GND U15 GND U16 GND U17 GND H10 VCC H11 VCC H16 ...
Page 154
... L9 VCCIO7 7 M8 VCCIO7 7 M9 VCCIO7 7 N8 VCCIO7 7 N9 VCCIO7 7 G13 VCCAUX - H20 VCCAUX - LatticeECP/EC Family Data Sheet Ball Ball Dual Function Number Function J14 VCCIO1 J15 VCCIO1 J16 VCCIO1 J17 VCCIO1 K17 VCCIO2 K18 VCCIO2 L18 VCCIO2 M18 VCCIO2 N18 ...
Page 155
... VCCAUX - Y13 VCCAUX - Y7 VCCAUX - 1 K19 VCC - 1 L8 VCC - 1 U19 VCC - 1 U8 VCC - 1. Tied to V CCPLL. LatticeECP/EC Family Data Sheet Ball Ball Dual Function Number Function H7 VCCAUX J19 VCCAUX J8 VCCAUX K7 VCCAUX L20 VCCAUX M20 VCCAUX M7 VCCAUX N20 VCCAUX P20 VCCAUX P7 VCCAUX T20 ...
Page 156
... For further information regarding Thermal Management, refer to the following located on the Lattice website at www.latticesemi.com. • Thermal Management document • Technical Note TN1052 - Power Estimation and Management for LatticeECP/EC and LatticeXP Devices • Power Calculator tool included with Lattice’s ispLEVER design tool standalone download from www.latticesemi.com/software LatticeECP/EC Family Data Sheet 4-80 ...
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... The markings appear as follows: © 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 158
... LFEC1E-3T100C 67 LFEC1E-4T100C 67 LFEC1E-5T100C 67 Part Number I/Os LFEC3E-3F256C 160 LFEC3E-4F256C 160 LFEC3E-5F256C 160 LFEC3E-3Q208C 145 LFEC3E-4Q208C 145 LFEC3E-5Q208C 145 LFEC3E-3T144C 97 LFEC3E-4T144C 97 LFEC3E-5T144C 97 LFEC3E-3T100C 67 LFEC3E-4T100C 67 LFEC3E-5T100C 67 Part Number I/Os LFEC6E-3F484C 224 LFEC6E-4F484C 224 LFEC6E-5F484C 224 LFEC6E-3F256C 195 LFEC6E-4F256C 195 LFEC6E-5F256C 195 LFEC6E-3Q208C 147 ...
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... LFEC20E-3F484C 360 LFEC20E-4F484C 360 LFEC20E-5F484C 360 Part Number I/Os LFEC33E-3F672C 496 LFEC33E-4F672C 496 LFEC33E-5F672C 496 LFEC33E-3F484C 360 LFEC33E-4F484C 360 LFEC33E-5F484C 360 LatticeECP/EC Family Data Sheet LatticeEC Commercial (Continued) Grade Package -4 fpBGA -5 fpBGA -3 PQFP -4 PQFP -5 PQFP Grade Package -3 fpBGA -4 fpBGA -5 fpBGA ...
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... I/Os LFECP20E-3F672C 400 LFECP20E-4F672C 400 LFECP20E-5F672C 400 LFECP20E-3F484C 360 LFECP20E-4F484C 360 LFECP20E-5F484C 360 Part Number I/Os LFECP33E-3F672C 496 LFECP33E-4F672C 496 LFECP33E-5F672C 496 LatticeECP/EC Family Data Sheet LatticeECP Commercial Grade Package Pins -3 fpBGA 484 -4 fpBGA 484 -5 fpBGA 484 -3 fpBGA 256 -4 fpBGA 256 -5 ...
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... LFEC1E-3Q208I 112 LFEC1E-4Q208I 112 LFEC1E-3T144I 97 LFEC1E-4T144I 97 LFEC1E-3T100I 67 LFEC1E-4T100I 67 Part Number I/Os LFEC3E-3F256I 160 LFEC3E-4F256I 160 LFEC3E-3Q208I 145 LFEC3E-4Q208I 145 LFEC3E-3T144I 97 LFEC3E-4T144I 97 LFEC3E-3T100I 67 LFEC3E-4T100I 67 Part Number I/Os LFEC6E-3F484I 224 LFEC6E-4F484I 224 LFEC6E-3F256I 195 LFEC6E-4F256I 195 LFEC6E-3Q208I 147 LFEC6E-4Q208I 147 LFEC6E-3T144I 97 LFEC6E-4T144I 97 Part Number ...
Page 162
... LFECP10E-4F484I 288 LFECP10E-3F256I 195 LFECP10E-4F256I 195 LFECP10E-3Q208I 147 LFECP10E-4Q208I 147 Part Number I/Os LFECP15E-3F484I 352 LFECP15E-4F484I 352 LFECP15E-3F256I 195 LFECP15E-4F256I 195 LatticeECP/EC Family Data Sheet LatticeEC Industrial (Continued) Grade Package -3 fpBGA -4 fpBGA -3 fpBGA -4 fpBGA Grade Package -3 fpBGA -4 fpBGA -3 fpBGA -4 fpBGA ...
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... Lattice Semiconductor Part Number I/Os LFECP20E-3F672I 400 LFECP20E-4F672I 400 LFECP20E-3F484I 360 LFECP20E-4F484I 360 Part Number I/Os LFECP33E-3F672I 496 LFECP33E-4F672I 496 LFECP33E-3F484I 360 LFECP33E-4F484I 360 LatticeECP/EC Family Data Sheet LatticeECP Industrial (Continued) Grade Package -3 fpBGA -4 fpBGA -3 fpBGA -4 fpBGA Grade Package -3 fpBGA -4 fpBGA -3 fpBGA -4 ...
Page 164
... LFEC1E-3TN100C 67 LFEC1E-4TN100C 67 LFEC1E-5TN100C 67 Part Number I/Os LFEC3E-3FN256C 160 LFEC3E-4FN256C 160 LFEC3E-5FN256C 160 LFEC3E-3QN208C 145 LFEC3E-4QN208C 145 LFEC3E-5QN208C 145 LFEC3E-3TN144C 97 LFEC3E-4TN144C 97 LFEC3E-5TN144C 97 LFEC3E-3TN100C 67 LFEC3E-4TN100C 67 LFEC3E-5TN100C 67 Part Number I/Os LFEC6E-3FN484C 224 LFEC6E-4FN484C 224 LFEC6E-5FN484C 224 LFEC6E-3FN256C 195 LFEC6E-4FN256C 195 LFEC6E-5FN256C 195 LFEC6E-3QN208C 147 ...
Page 165
... LFEC20E-5FN484C 360 Part Number I/Os LFEC33E-3FN672C 496 LFEC33E-4FN672C 496 LFEC33E-5FN672C 496 LFEC33E-3FN484C 360 LFEC33E-4FN484C 360 LFEC33E-5FN484C 360 LatticeECP/EC Family Data Sheet LatticeEC Commercial (Continued) Grade Package -4 Lead-Free fpBGA -5 Lead-Free fpBGA -3 Lead-Free PQFP -4 Lead-Free PQFP -5 Lead-Free PQFP Grade Package -3 Lead-Free fpBGA ...
Page 166
... LFECP20E-4FN672C 400 LFECP20E-5FN672C 400 LFECP20E-3FN484C 400 LFECP20E-4FN484C 400 LFECP20E-5FN484C 400 Part Number I/Os LFECP33E-3FN672C 496 LFECP33E-4FN672C 496 LFECP33E-5FN672C 496 LatticeECP/EC Family Data Sheet LatticeECP Commercial Grade Package Pins/Balls -3 Lead-Free fpBGA -4 Lead-Free fpBGA -5 Lead-Free fpBGA -3 Lead-Free fpBGA -4 Lead-Free fpBGA -5 Lead-Free fpBGA -3 Lead-Free PQFP ...
Page 167
... LFECP33E-5FN484C 360 Part Number I/Os LFEC1E-3QN208I 112 LFEC1E-4QN208I 112 LFEC1E-3TN144I 97 LFEC1E-4TN144I 97 LFEC1E-3TN100I 67 LFEC1E-4TN100I 67 Part Number I/Os LFEC3E-3FN256I 160 LFEC3E-4FN256I 160 LFEC3E-3QN208I 145 LFEC3E-4QN208I 145 LFEC3E-3TN144I 97 LFEC3E-4TN144I 97 LFEC3E-3TN100I 67 LFEC3E-4TN100I 67 Part Number I/Os LFEC6E-3FN484I 224 LFEC6E-4FN484I 224 LFEC6E-3FN256I 195 LFEC6E-4FN256I 195 LFEC6E-3QN208I ...
Page 168
... LFECP10E-4FN256I 195 LFECP10E-3QN208I 147 LFECP10E-4QN208I 147 Part Number I/Os LFECP15E-3FN484I 352 LFECP15E-4FN484I 352 LFECP15E-3FN256I 195 LFECP15E-4FN256I 195 LatticeECP/EC Family Data Sheet LatticeEC Industrial (Continued) Grade Package -3 Lead-Free fpBGA -4 Lead-Free fpBGA -3 Lead-Free fpBGA -4 Lead-Free fpBGA Grade Package -3 Lead-Free fpBGA -4 Lead-Free fpBGA ...
Page 169
... LFECP20E-4FN672I 400 LFECP20E-3FN484I 400 LFECP20E-4FN484I 400 Part Number I/Os LFECP33E-3FN672I 496 LFECP33E-4FN672I 496 LFECP33E-3FN484I 360 LFECP33E-4FN484I 360 LatticeECP/EC Family Data Sheet LatticeECP Industrial (Continued) Grade Package -3 Lead-Free fpBGA -4 Lead-Free fpBGA -3 Lead-Free fpBGA -4 Lead-Free fpBGA Grade Package -3 Lead-Free fpBGA -4 Lead-Free fpBGA ...
Page 170
... PCI: ww.pcisig.com © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 171
... Pinout Information Ordering Information © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 172
... Timing adders have been updated (rev. G 0.27). sysCONFIG port timing specifications have been updated. Pin Information Summary table has been updated. Power Supply and NC Connection table has been updated. OPN list has been updated. 7-2 Revision History LatticeECP/EC Family Data Sheet Change Summary , I ) has been updated ...
Page 173
... G 0.28). LatticeECP/EC Internal Switching Characteristics table has been updated (rev. G 0.28). LatticeECP/EC Family Timing Adders have been updated (rev. G 0.28). sysCLOCK PLL timing table has been updated (rev. G 0.28) LatticeECP/EC sysCONFIG Port Timing specification table has been updated (rev. G 0.28). ...
Page 174
... Section II. LatticeECP/EC Family Technical Notes ...
Page 175
... Lattice EC/ECP and LatticeXP devices. © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 176
... RSDS 2.375 1. Inputs on chip. Outputs are implemented with the addition of external resistors. sysIO Banking Scheme LatticeECP/EC and LatticeXP devices have eight programmable sysIO banks, two per side. Each sysIO bank has a V supply voltage and two reference voltages, V CCIO fer pair consists of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and ref- erenced) ...
Page 177
... REF1 pins is pre-determined within the bank. These pins REF voltage. REF input must be used as the reference voltage for the DQS and DQ REF1 and GND is used to generate an on-chip reference volt- REF1 8-3 LatticeECP/EC and LatticeXP sysIO Usage Guide V CCIO2 V REF1(2) V REF2(2) GND V ...
Page 178
... For more information on the DQS transition detect logic and its implementation please refer to REF2. Lattice technical note number TN1050, LatticeECP/EC DDR Usage Guide. Mixed Voltage Support in a Bank The LatticeECP/EC and LatticeXP sysIO buffer is connected to three parallel ratioed input buffers. These three par- allel buffers are connected to V CCIO, as fixed thresholds for 3.3V (V ...
Page 179
... I/O independently. The drive strength setting available are 2mA, 4mA, 6mA, 8mA, 12mA, 16mA and 20mA. Actual options available vary by the I/O voltage. The user must consider the maximum allowable current per bank and the package thermal limit current when selecting the drive strength. LatticeECP/EC and LatticeXP Right Side Bottom Side ...
Page 180
... The actual impedance matching may vary on the transmission line design and the load. To find the best matching recommended to drive the transmission line with different combinations of I/O standards and drive strengths that best match the line impedance. Lattice provides IBIS buffer models for the users to further analyze the imped- ance matching. ...
Page 181
... OPENDRAIN attribute in the software. The software implements open drain in the LatticeECP/EC and LatticeXP devices by connecting the data and tristate input of the output buffer. Software will implement open drain using this method for simple output buffers. If the user wants to assign open drain functionality to a bidirectional I/O, a similar implementation is required in the HDL design ...
Page 182
... EXT 8-8 LatticeECP/EC and LatticeXP sysIO Usage Guide V CCIO PCI Clamp Diode between 2.5V to 3.3V. is 2.75V. CCIO = 3.75 - 2.75 =1V Units µA µA µ ...
Page 183
... There is no separate attribute to set the V I/O types )/I = (5.25V - 3.75V)/27.4 = 54.8 ohm EXT INMAX D required to set these I/O standards are embedded in CCIO CCIO 8-9 LatticeECP/EC and LatticeXP sysIO Usage Guide requirements. Table 8-6 lists the available ...
Page 184
... LVCMOS and LVTTL I/O standards can be set to Open Drain configuration by using the OPENDRAIN attribute. Values: ON, OFF Default: OFF DRIVE The drive strength attribute is available for LVTTL and LVCMOS output standards. These can be set or each I/O pin individually. LatticeECP/EC and LatticeXP IO_TYPE LVCMOS12 LVCMOS25 LVDS25 RSDS ...
Page 185
... I/O registers if applicable. The user can turn this OFF by using the synthesis attribute or using the preference editor of the software. These attributes can only be applied on registers. CCIO. CCIO V CCIO 1.2 V 1 8-11 LatticeECP/EC and LatticeXP sysIO Usage Guide Table 8-7 shows the drive strength available Voltages 2 ...
Page 186
... All banks support emulated differential buffers using external resistor pack and complementary LVCMOS drivers. • In LatticeXP devices, not all PIOs have LVDS capability. Only four out of every seven I/Os can provide LVDS buffer capability. In LatticeECP/EC devices, there are no restrictions on the number of I/Os that can support LVDS ...
Page 187
... True LVDS (LVDS25) drivers are available on the left and right side of the devices. LVDS input support is provided on all sides of the device. All four sides support LVDS using complementary LVCMOS drivers with external resis- tors (LVDS25E). Please refer to the LatticeECP/EC and LatticeXP data sheets for a more detailed explanation of these LVDS imple- mentations. BLVDS All single-ended sysIO buffer pairs in the LatticeECP family support the Bus-LVDS standard using complementary LVCMOS drivers with external resistors ...
Page 188
... Lattice Semiconductor Internet: www.latticesemi.com LatticeECP/EC and LatticeXP 8-14 sysIO Usage Guide ...
Page 189
... Declaration*** ATTRIBUTE IO_TYPE: string; --***IO_TYPE assignment for I/O Pin*** ATTRIBUTE IO_TYPE OF portA: ATTRIBUTE IO_TYPE OF portB: ATTRIBUTE IO_TYPE OF portC: ® and Precision Syntax SIGNAL IS “PCI33”; SIGNAL IS “LVCMOS33”; SIGNAL IS “LVDS25”; 8-15 LatticeECP/EC and LatticeXP sysIO Usage Guide ® RTL Synthesis ...
Page 190
... SLEWRATE assignment for I/O Pin*** ATTRIBUTE SLEWRATE OF portB: SIGNAL IS “FAST”; FIXEDDELAY --***Attribute Declaration*** ATTRIBUTE FIXEDDELAY: string; --*** SLEWRATE assignment for I/O Pin*** ATTRIBUTE FIXEDDELAY OF portB: SIGNAL IS “TRUE”; SIGNAL IS "DOWN"; SIGNAL IS "UP"; SIGNAL IS "ON"; 8-16 LatticeECP/EC and LatticeXP sysIO Usage Guide ...
Page 191
... I/O Pin*** ATTRIBUTE din OF input_vector: SIGNAL IS “ “; ATTRIBUTE dout OF output_vector: SIGNAL IS “ “; LOC --***Attribute Declaration*** ATTRIBUTE LOC : string; --*** LOC assignment for I/O Pin*** ATTRIBUTE LOC OF input_vector: SIGNAL IS “E3,B3,C3 “; LatticeECP/EC and LatticeXP 8-17 sysIO Usage Guide ...
Page 192
... PinType PinName /* synthesis PCICLAMP =” PCIClamp Value”*/; PinType PinName /* synthesis SLEWRATE=”Slewrate Value”*/; PinType PinName /* synthesis FIXEDDELAY=”Fixeddelay Value”*/; PinType PinName /* synthesis DIN=” “*/; PinType PinName /* synthesis DOUT=” “*/; PinType PinName /* synthesis LOC=”pin_locations “*/; 8-18 LatticeECP/EC and LatticeXP sysIO Usage Guide ...
Page 193
... Lattice Semiconductor //I/O pin location input [3:0] DATA0 /* synthesis loc=”E3,B1,F3”*/; //Register pin location reg data_in_ch1_buf_reg3 /* synthesis loc=”R40C47” */; //Vectored internal bus reg [3:0] data_in_ch1_reg /*synthesis loc =”R40C47,R40C46,R40C45,R40C44” */; LatticeECP/EC and LatticeXP 8-19 sysIO Usage Guide ...
Page 194
... PinName DRIVE Drive Value //pragma attribute PinName IO_TYPE Pullmode Value //pragma attribute PinName PCICLAMP PCIClamp Value //pragma attribute PinName IO_TYPE Slewrate Value //pragma attribute PinName IO_TYPE Fixeddelay Value //pragma attribute PinName LOC pin_location 8-20 LatticeECP/EC and LatticeXP sysIO Usage Guide ...
Page 195
... Lattice Semiconductor // ***Fixeddelay*** // pragma attribute load FIXEDDELAY TRUE //***LOC*** //pragma attribute portB loc E3 LatticeECP/EC and LatticeXP 8-21 sysIO Usage Guide ...
Page 196
... Figure 8-4 and Figure 8-5 show the Pin Attribute Sheet and the Cell Attribute Sheet views of the Preference Editor. For further information on how to use the Preference Editor, refer to the ispLEVER Help documentation located in the Help menu option of the software. Figure 8-4. Pin Attributes Tab Figure 8-5. Cell Attributes Tab LatticeECP/EC and LatticeXP 8-22 sysIO Usage Guide ...
Page 197
... Note: If the comp_name, macro_name, or site_name begins with anything other than an alpha character (for exam- ple, “11C7”), you must enclose the name in quotes. Wildcard expressions are allowed in <comp_name>. Example This command places the port Clk0 on the site A4: LatticeECP/EC and LatticeXP 8-23 sysIO Usage Guide ...
Page 198
... PGROUP “vref_pg2” VREF “ref2” COMP “al(0)” COMP “al(1)” COMP “al(2)” COMP “al(3)” COMP “al(4)” COMP “al(5)” COMP “al(6)” COMP “al(7)”; LOCATE VREF “ref1” SITE PR29C; LatticeECP/EC and LatticeXP 8-24 sysIO Usage Guide ...
Page 199
... Lattice Semiconductor LOCATE VREF “ref2” SITE PR48B; or LOCATE PGROUP “ vref_pg1” BANK 2; LOCATE PGROUP “ vref_pg2” BANK 2; LatticeECP/EC and LatticeXP 8-25 sysIO Usage Guide ...
Page 200
... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...