LFEC3E-3QN208I Lattice, LFEC3E-3QN208I Datasheet - Page 348

• Manufacturer Part Number: LFEC3E-3QN208I
• Description: IC FPGA 3KLUTS 208PQFP
• Manufacturer: Lattice
• Series: EC3r

Specifications of LFEC3E-3QN208I

• Number Of Logic Elements/cells: 3100
• Number Of Labs/clbs: -
• Total Ram Bits: 56320
• Number Of I /o: 145
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q6377645

Lattice Semiconductor
LatticeECP/EC sysCONFIG Usage Guide
If the LatticeECP/EC device is the only device in the chain, or the last device in a chain, the wake-up process
should be initiated by the completion of the configuration. Once the configuration is complete the internal Done Bit
will be set and the wake-up process will begin.
Synchronous to External DONE Signal
The DONE Pin can be selected to delay wake up. If DONE_EX is true the wake-up sequence will be delayed until
the DONE pin is driven high externally, then the device will follow the selected wake-up sequence.
Wake-up Clock Selection
The wake-up sequence is synchronized to a clock source, the user can select the clock source for wake up. The
clock sources are CCLK, TCK and User Clock. The default clock is TCK if using ispJTAG, and CCLK if using sys-
CONFIG. The User Clock is chosen at the time of design. The user can select any of the CLK pins of the device or
a net (routing node) as the User Clock source. The WAKEUP_CLK shall default to CCLK or TCK.
Read Back
Read Sequence
To read the configuration memory data or register contents back, WRITEN is first set to low to send the read
instruction into the device. The device will read in the command from the host and execute the command once read
in. If the LatticeECP/EC device cannot have the data ready by the next clock cycle, it will drive the BUSY pin high.
When BUSY is high, the device will continue to execute the command regardless of the state of the CSN or CS1N
pins. The device will drive the BUSY pin low when the data is ready but will not drive the D[0:7] until the CSN and
CS1N pins are pulled low by the host. The WRITEN pin should be pulled high after sending in the command. The
CSN, CS1N and WRITEN signals are latched and the device will switch to read mode on the rising edge of CCLK.
If the LatticeECP/EC device needs more than one clock cycle to switch the bus around, BUSY will be kept high until
the D[0:7] is ready.
As in the Write sequence, CSN and CS1N signals can be used to temporarily pause the read sequence in case the
host system is busy. The data is read at the next rising CCLK edge, after CSN and CS1N pins are set to low and
the BUSY pin is low.
Transparent Read Back
Using the Slave Parallel Mode for read back, the user I/Os will remain functional. The Slave Parallel port pins must
be retained in order to allow read back by setting the PERSISTENT preference to ON. CCLK becomes input only.
The user must ensure that User Mode read/write operations from/to the EBR and distributed RAM do not interfere
with the transparent read back.
Configuration Mode Read Back
Read back can also be done with the LatticeECP/EC device in configuration mode. Only the Slave Parallel Mode is
supported for configuration read back. By driving the WRITEN pin high, the Slave Parallel port will watch for the
read back request from the host device.
Software Control
In order to control the configuration of the LatticeECP/EC device beyond the default settings, software preferences
can be used. Table 12-4 is a list of the preference, the default settings and the section more information about the
preference can be found.
12-15