PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 68

• Manufacturer Part Number: PEF82912FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PEF82912FV1.4

• Mounting Style: SMD/SMT
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

•
Figure 28
When the TIC bus is seized by the Q-SMINT I, the bus is identified to other devices as
occupied via the DU Ch2 Bus Accessed-bit state ’0’ until the access request is
withdrawn. After a successful bus access, the Q-SMINT I is automatically set into a
lower priority class, that is, a new bus access cannot be performed until the status "bus
free" is indicated in two successive frames.
If none of the devices connected to the IOM -2 interface request access to the D and C/
I0 channels, the TIC bus address 7 will be present. The device with this address will
therefore have access, by default, to the D and C/I0 channels.
Note: Bit BAC (CIX0 register) should be reset by the
2.3.5.3
The availability of the DU D channel is indicated in bit 5 "Stop/Go" (S/G) of the last octet
in DD channel 2
MODEH.DIM2-0=0x1.
S/G = 1 : stop
S/G = 0 : go
The Stop/Go bit is available to other layer-2 devices connected to the IOM -2 interface
to determine if they can access the D channel in upstream direction.
Data Sheet
requested, to grant other devices access to the D and C/I0 channels.
DU
Stop/Go Bit Handling
Structure of Last Octet of Ch2 on DU
B1
(Figure
B2
MON0
29). The arbitration mechanism must be activated by setting
D CI0
MR
MX
IC1
54
IC2
BAC
MON1
TIC-BUS Address (TAD 2 - 0)
Bus Accessed ("1" no TIC-BUS Access)
2
CI1
TAD
1
0
C when access is no more
MR
MX
Functional Description
PEF 82912/82913
TAD
BAC
ITD02575.vsd
2001-03-30