PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 171

• Manufacturer Part Number: PEF82912FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PEF82912FV1.4

• Mounting Style: SMD/SMT
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

MFEN
SQX1-4
4.7.7
ISTAS
Value after reset: 00
x
LD
RIC
Data Sheet
These bits are set if an interrupt status occurs and an interrupt signal is activated if the
corresponding mask bit is set to “0”. If the mask bit is set to “1” no interrupt is generated,
however the interrupt status bit is set in ISTAS. RIC, SQC and SQW are cleared by
reading the corresponding source register S_STA, SQRR or writing SQXR,
respectively.
7
x
ISTAS - Interrupt Status Register S-Transceiver
Multiframe Enable
Used to enable or disable the multiframe structure.
0 =
1 =
Transmitted S/Q Bits
Transmitted S bits in frames 1, 6, 11 and 16
Reserved
Level Detection
0 =
1 =
Receiver INFO Change
0 =
1 =
x
S/T multiframe is disabled
S/T multiframe is enabled
inactive
Any receive signal has been detected on the line. This bit is set to
“1” (i.e. an interrupt is generated if not masked) as long as any
receive signal is detected on the line.
inactive
RIC is activated if one of the S_STA bits RINF or ICV has changed.
H
x
x
read
157
LD
RIC
Register Description
PEF 82912/82913
Address:
SQC
2001-03-30
SQW
0
38
H