PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 48

• Manufacturer Part Number: PEF82912FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PEF82912FV1.4

• Mounting Style: SMD/SMT
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

PEF 82912/82913
Functional Description
Figure 14
shows the timing of looping TSa from DU to DD via CDAxy register. TSa is
read in the CDAxy register from DU and is written one frame later on DD.
Figure 15
shows the timing of shifting data from TSa to TSb on DU(DD). In
Figure
15a)
shifting is done in one frame because TSa and TSb didn’t succeed directly one another
(a = 0...9 and b
a+2) In
Figure
15b) shifting is done from one frame to the following
frame. This is the case when the time slots succeed one other (b = a+1) or b is smaller
than a (b < a).
At looping and shifting the data can be accessed by the controller between the
synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). STI and
STOV are explained in the section ’Synchronous Transfer’. If there is no controller
intervention the looping and shifting is done autonomously.
•.
FSC
DU
TSa
TSa
CDAxy
*)
µC
DD
TSa
TSa
*) if access by the µC is required
Figure 14
Data Access when Looping TSa from DU to DD
Data Sheet
34
2001-03-30