PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 169

• Manufacturer Part Number: PEF82912FV1.4
• Description: ISDN Interface ISDN
• Manufacturer: Infineon Technologies

Specifications of PEF82912FV1.4

• Mounting Style: SMD/SMT
• Package / Case: MQFP-64
• Lead Free Status / Rohs Status: Details

4.7.4
S_ CMD
Value after reset: 08
Important: This register - except bit DPRIO - is writable only if the Layer 1 state machine
of the device is disabled (S_CONF0.L1SW = 1) and implemented in software! With the
device layer 1 state machine enabled, the signals from this register are automatically
generated. DPRIO can also be written in intelligent NT mode.
XINF
DPRIO
PD
LP_A
Data Sheet
7
S_CMD - S-Transceiver Command Register
Transmit INFO
000 =
001 =
010 =
011 =
100 =
101 =
11x =
D-Channel Priority
0 =
1 =
Power Down
0 =
1 =
Loop Analog
The setting of this bit corresponds to the C/I command ARL.
XINF
Transmit INFO 0
reserved
Transmit INFO 2
Send continuous pulses at 192 kbit/s alternating or 96 kHz
rectangular, respectively (TM2)
Send single pulses at 4 kbit/s with alternating polarity
corresponding to 2 kHz fundamental mode (TM1)
reserved
Priority class 1 for D channel access on IOM
Priority class 2 for D channel access on IOM
The transceiver is set to operational mode
The transceiver is set to power down mode
H
Transmit INFO 4
DPRIO
read/write
155
1
PD
Register Description
PEF 82912/82913
LP_A
Address:
2001-03-30
0
0
34
H