PEF82912FV1.4 Infineon Technologies, PEF82912FV1.4 Datasheet - Page 180

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PEF82912FV1.4

Manufacturer Part Number
PEF82912FV1.4
Description
ISDN Interface ISDN
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF82912FV1.4

Mounting Style
SMD/SMT
Package / Case
MQFP-64
Lead Free Status / Rohs Status
 Details

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4.9.2
XXX_TSDPxy
Register
CDA_TSDP10
CDA_TSDP11
CDA_TSDP20
CDA_TSDP21
S_TSDP_B1
S_TSDP_B2
This register determines the time slots and the data ports on the IOM
data channels xy of the functional units XXX (Controller Data Access (CDA) and S-
transceiver (S)).
Note: The U-transceiver is always in IOM-2 channel 0.
DPS
TSS
Data Sheet
Note: For the CDA (controller data access) data the input is determined by the
CDAx_CR.SWAP bit. If SWAP = ‘0’ the input for the CDAxy data is vice versa to
the output setting for CDAxy. If the SWAP = ‘1’ the input from CDAx0 is vice
versa to the output setting of CDAx1 and the input from CDAx1 is vice versa to
the output setting of CDAx0.
DPS
7
XXX_TSDPxy - Time Slot and Data Port Selection for CHxy
Data Port Selection
0 =
1 =
Timeslot Selection
Selects one of the 12 timeslots from 0...11 on the IOM
data channels.
0
The data channel xy of the functional unit XXX is output on DD.
The data channel xy of the functional unit XXX is input from DU.
The data channel xy of the functional unit XXX is output on DU.
The data channel xy of the functional unit XXX is input from DD.
Value after Reset
00
01
80
81
reserved
84
85
H
H
H
H
H
H
(= output on B1-DD)
(= output on B2-DD)
(= output on B1-DU)
(= output on B2-DU)
(= output on TS4-DU)
(= output on TS5-DU)
0
0
read/write
166
Register Address
44
45
46
47
48-4B
4C
4D
H
H
H
H
H
H
H
TSS
Register Description
®
PEF 82912/82913
-2 interface for the
®
-2 Interface for the
Address: 44-4D
2001-03-30
0
H

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